4.4 Reset Structure

In this design, the reset signal of the PRBS generator and the PRBS checker, are issued using the Reset_logic module. The Reset_sync_tx_0 (CoreReset_PF) module releases active-low reset of data generator block when the TX_CLK_STABLE signal from the PF_XCVR interface and the DEVICE_INIT_DONE signal from the PF_INIT_MONITOR block are asserted.

Similarly, the Reset_sync_rx_0 (CoreReset_PF) module releases active-low reset of data checker when the RX_READY signal from the PF_XCVR interface and the DEVICE_INIT_DONE signal from the PF_INIT_MONITOR block are asserted.

The previous setup ensures that the PRBS generation and PRBS checker does not start until TX_clock_stable and LANEO_RX_VAL are asserted respectively.

The DEVICE_INIT_DONE signal is asserted when the device initialization is completed. For more information about device initialization, see PolarFire Family Power-Up and Resets User Guide .

For more information on CoreReset_PF IP core, see CoreReset_PF from the Libero® SoC catalog.

The following figure shows the reset structure in this design.