4.2 Port Description
(Ask a Question)The following table lists the port signals for this design.
| Signal | Direction | Description |
|---|---|---|
| REF_CLK_PAD_P and REF_CLK_PAD_N | Input | Differential reference clock is generated from the on-board 125 MHz oscillator |
| LANE0_RXD_N | Input | Transceiver receiver differential input |
| LANE0_RXD_P | Input | Transceiver receiver differential input |
| SWITCH | Input | DIP switch setting to initiate DFE calibration trigger for DFE calibration is also generated by user design using the condition (RX_READY and RX_IDLE) |
| LANE0_TXD_N | Output | Transceiver transmitter differential output |
| LANE0_TXD_P | Output | Error flag generated from PRBS checker module when there is data mismatch |
| error_out | Output | Dynamic CCC OUT3 Fabric Clock |
| Lock | Output | Lock signal flag generated from PRBS checker module when there is data match |
| DFE_CAL_DONE | Output | Output signal goes HIGH to indicate that DFE calibration is done |
| LANE0_CALIBRATING | Output | Output signal goes HIGH to indicate that the DFE/CDR is calibrating |