6.2 Set Page Address and Read Page Address Commands

The AT34C04 incorporates an innovative memory addressing technique that utilizes a Set Page Address (SPA) and Read Page Address (RPA) commands to select and verify the desired half of the memory enabled to perform write and read operations. Due to the requirement for A0 pin to be driven to V_HV, the SPA and the RPA commands are fully supported in a single DIMM (isolated DIMM) end application or a single DIMM programming station only.

Example: If SPA = 0, then the first-half or lower 256 bytes of the Serial EEPROM is selected allowing access to Quadrant 0 and Quadrant 1. Alternately, if SPA = 1, then the second-half or upper 256 bytes of the Serial EEPROM is selected allowing access to Quadrant 2 and Quadrant 3.

Setting the Set Page Address (SPA) value selects the desired half of the EEPROM for performing write or read operations. This is done by sending the SPA as seen in Figure 6-1. The SPA command sequence requires the master to transmit a Start condition followed by sending a device address byte of ‘011011*0’ where the ‘*’ in the bit 7 position will dictate which half of the EEPROM is being addressed. A ‘0’ in this position (or 6Ch) is required to set the page address to the first half of the memory and a ‘1’ (or 6Eh) is necessary to set the page address to the second half of the memory. After receiving the device address byte, the AT34C04 should return an ACK and the master should follow by sending two bytes of ‘don’t care’ values.

The JEDEC EE1004v specification allows for either an ACK or NACK response for each of the two data bytes. The AT34C04 responds with an ACK. An alternate part number is available for applications which expect a NACK response. For details, refer to Product Identification System. The protocol is completed by the master sending a Stop condition to end the operation.

Reading the state of the SPA can be accomplished via the Read Page Address (RPA) command. The master can issue the RPA command to determine if the AT34C04’s internal address counter is located in the first 2-Kbit section or the second 2-Kbit memory section based upon the device’s ACK or NACK response to the RPA command.

The RPA command sequence requires the master to transmit a Start bit followed by a device address byte of ‘01101101’ (6Dh). If the device’s current address counter (page address) is located in the first half of the memory, the AT34C04 responds with an ACK to the RPA command. Alternatively, a NACK response to the RPA command indicates the page address is located in the second half of the memory (see Figure 6-2).

Following the device address byte and the device’s ACK or NACK response, the AT34C04 should transmit two data bytes of ‘don’t care’ values. The master should NACK on these two data bytes followed by the master sending a Stop condition to end the operation.

After power-up, the SPA is set to zero indicating internal address counter is located in the first half of the memory. Performing a software Reset (see Software Reset) will also set the SPA to zero.

The AT34C04 incorporates a Reversible Software Write Protect (RSWP) feature that allows the ability to selectively write protect data stored in any or all of the four 128-byte quadrants. See Write Protection for more information on the RSWP feature.