6.1 Device Addressing
Accessing the device requires an 8-bit device address byte following a Start condition to enable the device for a read or write operation. Since multiple slave devices can reside on the serial bus, each slave device must have its own unique address so the master can access each device independently.
The Most Significant four bits of the device address byte is referred to as the device type
identifier. The device type identifier ‘1010
’ (Ah) for the main EEPROM
access, or ‘0110
’ (6h) for Page Address (see Set Page Address and Read
Page Address Commands) and Write Protection Registers (see Write Protection)
access is required in bits 7 through 4 of the device address byte (see Table 6-1).
Following the 4-bit device type identifier are the hardware slave address bits, A2, A1 and
A0. These bits can be used to expand the address space by allowing up to eight Serial
EEPROM devices on the same bus. These hardware slave address bits must correlate with the
voltage level on the corresponding hardwired device address input pins A0, A1 and A2. The
A0, A1 and A2 pins use an internal proprietary circuit that automatically biases the pin to
a logic ‘0
’ state if the pin is allowed to float. In order to operate in a
wide variety of application environments, the pull‑down mechanism is intentionally designed
to be somewhat strong. Once the pin is biased above the CMOS input buffer’s trip point
(~0.5 x VCC), the pull-down mechanism disengages. Microchip recommends
connecting the A0, A1 and A2 pins to a known state whenever possible.
The eighth bit (bit 0) of the device address byte is the Read/Write Select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low.
Upon the successful comparison of the device address byte, the AT34C04 will return an ACK. If a valid comparison is not made, the device will NACK.
Access Area | Device Type Identifier | Hardware Slave Address Bits | R/W Select | |||||
---|---|---|---|---|---|---|---|---|
Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 | |
EEPROM | 1 | 0 | 1 | 0 | A2 | A1 | A0 | R/W |
Write Protection and Page Address Functions | 0 | 1 | 1 | 0 | A2 | A1 | A0 | R/W |
For all operations except the current address read, a word address byte must be transmitted to the device immediately following the device address byte. The word address byte contains an 8-bit memory array word address, and is used to specify which byte location in the EEPROM to start reading or writing. Refer to Table 6-2 to review these bit positions.
Access Area | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
---|---|---|---|---|---|---|---|---|
EEPROM | A7 | A6 | A5 | A4 | A3 | A2 | A1 | A0 |
Set Page Address (SPA) | X | X | X | X | X | X | X | X |
Write Protection Register | X | X | X | X | X | X | X | X |