1.8.2 SPI Master Mode Programming

The embedded system controller contains a dedicated SPI block for programming, which can operate in master or slave mode. In master mode, the PolarFire SoC device interfaces are used to download programming data through the external SPI flash. In slave mode, the SPI block communicates with a remote device that initiates download of programming data to the device.

The following figure shows the board-level connectivity for SPI master mode programming in PolarFire SoC devices.

Figure 1-7. SPI Master Mode Programming

The following table lists the SPI master mode programming pins.

Table 1-14. SPI Master Mode Programming Pins
SPI Pin NameDirectionUnused ConditionDescription
SCKBidirectionalConnect to VSS through a 
10 kΩ resistorSPI clock.1
SSBidirectionalConnect to VSS through a 
10 kΩ resistorSPI slave select.1
SDIInputConnect to VDDI3 through a 
10 kΩ resistorSDI input.1
SDOOutputDNCSDO output.1
SPI_ENInputConnect to VSS

through a 10 kΩ resistor

SPI enable.

0: SPI output tri-stated

1: Enabled

Pulled up or down through a resistor or driven dynamically from an external source to enable or tri-state the SPI I/O.

IO_CFG_INTFInputConnect to VSS

through a 10 kΩ resistor

SPI I/O configuration.

0: SPI slave interface

1: SPI master interface

Pulled up or down through a resistor or driven dynamically from an external source to indicate whether the shared SPI is a master or slave.

(1) The SCK, SS, SDI, and SDO pins are shared between the system controller and the FPGA fabric. When the system controller’s SPI is enabled and configured as a master, the system controller hands over the control of the SPI to the fabric (after device power-up).