1.8.1 JTAG Programming
(Ask a Question)The JTAG interface is used for the device programming and testing, or for debugging the firmware. When the device reset (DEVRST_N) is asserted, JTAG I/Os are not accessible. JTAG I/Os are powered by Bank 3 VDDI.
The following figure shows the board-level connectivity for JTAG programming mode in PolarFire SoC devices.
The following table lists the JTAG pin names and descriptions.
| Pin Names | Direction | Unused Condition | Description |
|---|---|---|---|
| TMS | Input | DNC | JTAG test mode select. |
| TRSTB | Input | Must be connected to VDDI3 through a 1 kΩ resistor. | JTAG test reset. Must be held low during device operation. If JTAG is not used, an external pull-down resistor can be included to ensure that the TAP is held in reset mode. |
| TDI | Input | DNC | JTAG test data in |
| TCK | Input | Must be connected to VSS through a 10 kΩ resistor | JTAG test clock |
| TDO | Output | DNC | JTAG test data out |