1.4.1 MSS DDR I/Os
(Ask a Question)The MSS DDR I/Os are a dedicated set of pins for x32 width DDR interface with ECC support. The dedicated set of pins are as follows:
- MSS_DDR_DQ[0:35]
- MSS_DDR_DQSP[0:4], MSS_DDR_DQSN[0:4]
- MSS_DDR_DM[0:4]
- MSS_DDR_A[0:16]
- MSS_DDR_CK_0, MSS_DDR_CK_N0
- MSS_DDR_CK_1, MSS_DDR_CK_N1
- MSS_DDR_RAM_RST_N
- MSS_DDR_VREF_IN
- MSS_DDR_BA0, MSS_DDR_BA1
- MSS_DDR_BG0, MSS_DDR_BG1
- MSS_DDR_CS0, MSS_DDR_CS1
- MSS_DDR_CKE0, MSS_DDR_CKE1
- MSS_DDR_ODT0, MSS_DDR_ODT1
- MSS_DDR_ACT_N
- MSS_DDR_WE_N
- MSS_DDR_ALERT_N
- MSS_DDR_PARITY
The interface supports the following types of DDR memories:
- DDR4 – Single and Dual Rank
- DDR3 – Single and Dual Rank
- LPDDR4
- LPDDR3
For more details about pin mapping and DDR user models, see PolarFire SoC Packaging Pin Assignment Table (PPAT) and PolarFire FPGA and PolarFire SoC FPGA Memory Controller User Guide.