15.6 Maximum Clock Frequencies
Symbol | Description | Conditions | Fmax | Units | |
---|---|---|---|---|---|
PL0 | PL2 | ||||
Fgclkgen[0:2] | GCLK Generator output Frequency | - | 24 | 96 | MHz |
Fgclkgen[3:8] | undivided | 24 | 96 | MHz | |
Fgclkgen[3:8] | divided | 16 | 66 | MHz |
Note:
- These values are based on simulation. They are not covered by production test limits or characterization.
Symbol | Description | Conditions | Max. | Units | |
---|---|---|---|---|---|
PL0 | PL2 | ||||
fCPU | CPU clock frequency | - | 12 | 48 | MHz |
fAHB | AHB clock frequency | - | 12 | 48 | MHz |
fAPBA | APBA clock frequency | Bus clock domain = BACKUP | 6 | 6 | MHz |
fAPBA | APBA clock frequency | Bus clock domain = Low Power | 12 | 48 | MHz |
fAPBB | APBB clock frequency | - | 12 | 48 | MHz |
fAPBC | APBC clock frequency | - | |||
fAPBD | APBD clock frequency | - | |||
fAPBE | APBE clock frequency | - | |||
fGCLK_DFLL48M_REF | DFLL48M Reference clock frequency | - | NA | 33 | kHz |
fGCLK_DPLL | FDPLL96M Reference clock frequency | - | 2 | 2 | MHz |
fGCLK_DPLL_32K | FDPLL96M 32k Reference clock frequency | - | 32 | 100 | kHz |
fGCLK_EIC | EIC input clock frequency | - | 12 | 48 | MHz |
fGCLK_USB | USB input clock frequency | - | NA | 60 | MHz |
fGCLK_EVSYS_CHANNEL_0 | EVSYS channel 0 input clock frequency | - | 12 | 48 | MHz |
fGCLK_EVSYS_CHANNEL_1 | EVSYS channel 1 input clock frequency | - | |||
fGCLK_EVSYS_CHANNEL_2 | EVSYS channel 2 input clock frequency | - | |||
fGCLK_EVSYS_CHANNEL_3 | EVSYS channel 3 input clock frequency | - | |||
fGCLK_EVSYS_CHANNEL_4 | EVSYS channel 4 input clock frequency | - | |||
fGCLK_EVSYS_CHANNEL_5 | EVSYS channel 5 input clock frequency | - | |||
fGCLK_EVSYS_CHANNEL_6 | EVSYS channel 6 input clock frequency | - | |||
fGCLK_EVSYS_CHANNEL_7 | EVSYS channel 7 input clock frequency | - | |||
fGCLK_EVSYS_CHANNEL_8 | EVSYS channel 8 input clock frequency | - | |||
fGCLK_EVSYS_CHANNEL_9 | EVSYS channel 9 input clock frequency | - | |||
fGCLK_EVSYS_CHANNEL_10 | EVSYS channel 10 input clock frequency | - | |||
fGCLK_EVSYS_CHANNEL_11 | EVSYS channel 11 input clock frequency | - | |||
fGCLK_SERCOMx_SLOW | Common SERCOM slow input clock frequency | - | 1 | 5 | MHz |
fGCLK_SERCOM0_CORE | SERCOM0 input clock frequency | - | 12 | 48 | MHz |
fGCLK_SERCOM1_CORE | SERCOM1 input clock frequency | - | |||
fGCLK_SERCOM2_CORE | SERCOM2 input clock frequency | - | |||
fGCLK_SERCOM3_CORE | SERCOM3 input clock frequency | - | |||
fGCLK_SERCOM4_CORE | SERCOM4 input clock frequency | - | |||
fGCLK_SERCOM5_CORE | SERCOM5 input clock frequency | - | |||
fGCLK_TCC0, GCLK_TCC1 | TCC0,TCC1 input clock frequency | - | 24 | 96 | MHz |
fGCLK_TCC2, GCLK_TC0 | TCC2,TC0 input clock frequency | - | 12 | 48 | MHz |
fGCLK_TC1 | TC1 input clock frequency | - | |||
fGCLK_TC4 | TC4 input clock frequeny | - | |||
fGCLK_ADC | ADC input clock frequency | - | 12 | 48 | MHz |
fGCLK_AC | AC digital input clock frequency | - | |||
fGCLK_PTC | PTC input clock frequency | - | |||
fGCLK_CCL | CCL input clock frequency | - |
Note:
- These values are based on simulation. They are not covered by production test limits or characterization.