15.8 Wake-Up Time
Conditions:
- VDDIN = 3.3V
- LDO Regulation mode
- CPU clock = OSC16M at 12 MHz
- 1 Wait-state
- Cache enabled
- Flash Fast Wake up enabled (NVMCTRL.CTRLB.FWUP = 1)
- Flash in WAKEUPINSTANT mode (NVMCTRL.CTRLB.SLEEPPRM = 1)
For IDLE and STANDBY, CPU sets an IO by writing PORT->IOBUS without jumping in an interrupt handler (Cortex M0+ register PRIMASK = 1). The wake-up time is measured between the edge of the wake-up input signal and the edge of the GPIO pin.
For Backup, the exit of mode is done through RTC wake-up. The wake-up time is measured between the toggle of the RTC pin and the set of the IO done by the first executed instructions after reset.
Sleep Mode | Condition | Typ. | Unit | |
---|---|---|---|---|
IDLE | PL2 or PL0 | 1.2 | µs | |
STANDBY | PL0 PM.PLSEL.PLDIS = 1 (see errata 13674 for revision A) |
PDCFG default | 5.1 | µs |
PD012 forced active PDCFG = 3 | 2.1 | |||
PL2 Voltage scaling at default values: SUPC->VREG.VSVSTEP = 0 SUPC->VREG.VSPER = 0 |
PDCFG default | 76 | µs | |
PD012 forced active PDCFG = 3 | 75 | |||
PL2 Voltage scaling at fastest setting: SUPC->VREG.VSVSTEP = 15 SUPC->VREG.VSPER = 0 | PDCFG default | 16 | µs | |
PD012 forced active PDCFG = 3 | 15 | µs | ||
BACKUP | — | 90 | µs |