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IEEE 802.15.4 Sub-GHz System-in-Package Datasheet
IEEE 802.15.4 Sub-GHz System-in-Package Datasheet
  1. Home
  2. 13 Reference Guide - SAM L21
  3. 13.22 SERCOM I2C – SERCOM Inter-Integrated Circuit
  4. 13.22.6 Functional Description
  5. 13.22.6.2 Basic Operation
  6. 13.22.6.2.4 I2C Master Operation
  7. 13.22.6.2.4.1 Master Clock Generation
  • Introduction
  • Features
  • 1 Description
  • 2 Configuration Summary
  • 3 Ordering Information
  • 4 System Introduction
  • 5 Pinout
  • 6 Signal Description

    Functional description of signals available at the package or routed in between the system dies.

  • 7 I/O Multiplexing and Considerations
  • 8 Power Supply and Start-Up Considerations
  • 9 Product Mapping
  • 10 Memories
  • 11 Processor and Architecture
  • 12 Application Schematic Introduction

  • 13 Reference Guide - SAM L21
    • 13.1 PAC - Peripheral Access Controller
    • 13.2 Peripherals Configuration Summary
    • 13.3 DSU - Device Service Unit
    • 13.4 Clock System
    • 13.5 GCLK - Generic Clock Controller

    • 13.6 MCLK – Main Clock
    • 13.7 RSTC – Reset Controller
    • 13.8 PM – Power Manager
    • 13.9 OSCCTRL – Oscillators Controller
    • 13.10 OSC32KCTRL – 32KHz Oscillators Controller
    • 13.11 SUPC – Supply Controller
    • 13.12 WDT – Watchdog Timer
    • 13.13 RTC – Real-Time Counter
    • 13.14 DMAC – Direct Memory Access Controller
    • 13.15 EIC – External Interrupt Controller
    • 13.16 NVMCTRL – Non-Volatile Memory Controller
    • 13.17 PORT - I/O Pin Controller
    • 13.18 EVSYS – Event System
    • 13.19 SERCOM – Serial Communication Interface
    • 13.20 SERCOM USART – SERCOM Universal Synchronous and Asynchronous Receiver and Transmitter
    • 13.21 SERCOM SPI – SERCOM Serial Peripheral Interface
    • 13.22 SERCOM I2C – SERCOM Inter-Integrated Circuit
      • 13.22.1 Overview
      • 13.22.2 Features
      • 13.22.3 Block Diagram
      • 13.22.4 Signal Description
      • 13.22.5 Product Dependencies
      • 13.22.6 Functional Description
        • 13.22.6.1 Principle of Operation
        • 13.22.6.2 Basic Operation
          • 13.22.6.2.1 Initialization
          • 13.22.6.2.2 Enabling, Disabling, and Resetting
          • 13.22.6.2.3 I2C Bus State Logic
          • 13.22.6.2.4 I2C Master Operation
            • 13.22.6.2.4.1 Master Clock Generation
              • 13.22.6.2.4.1.1 Clock Generation (Standard-Mode, Fast-Mode, and Fast-Mode Plus)
              • 13.22.6.2.4.1.2 Master Clock Generation (High-Speed Mode)
            • 13.22.6.2.4.2 Transmitting Address Packets
            • 13.22.6.2.4.3 Transmitting Data Packets
            • 13.22.6.2.4.4 Receiving Data Packets (SCLSM=0)
            • 13.22.6.2.4.5 Receiving Data Packets (SCLSM=1)
            • 13.22.6.2.4.6 High-Speed Mode
            • 13.22.6.2.4.7 10-Bit Addressing
          • 13.22.6.2.5 I2C Slave Operation
        • 13.22.6.3 Additional Features
        • 13.22.6.4 DMA, Interrupts and Events
        • 13.22.6.5 Sleep Mode Operation
        • 13.22.6.6 Synchronization
      • 13.22.7 Register Summary - I2C Slave
      • 13.22.8 Register Description - I2C Slave
      • 13.22.9 Register Summary - I2C Master
      • 13.22.10 Register Description - I2C Master
    • 13.23 TC – Timer/Counter
    • 13.24 TCC – Timer/Counter for Control Applications
    • 13.25 USB – Universal Serial Bus
    • 13.26 CCL – Configurable Custom Logic
    • 13.27 ADC – Analog-to-Digital Converter
    • 13.28 AC – Analog Comparators
    • 13.29 PTC - Peripheral Touch Controller
    • 13.30 RFCTRL – AT86RF212B Front-End Control Signal Interface
  • 14 Reference Guide - AT86RF212B
  • 15 Electrical Characteristics
  • 16 Packaging Information
  • 17 Schematic Checklist
  • 18 Design Considerations
  • 19 Conventions
  • 20 Acronyms and Abbreviations
  • 21 Continuous Transmission Test Mode
  • 22 Errata
  • 23 References
  • 24 Document Revision History
  • The Microchip Website
  • Product Change Notification Service
  • Customer Support
  • Microchip Devices Code Protection Feature
  • Legal Notice
  • Trademarks
  • Quality Management System
  • Worldwide Sales and Service

13.22.6.2.4.1 Master Clock Generation

The SERCOM peripheral supports several I2C bi-directional modes:
  • Standard mode (Sm) up to 100kHz
  • Fast mode (Fm) up to 400kHz
  • Fast mode Plus (Fm+) up to 1MHz
  • High-speed mode (Hs) up to 3.4MHz
The Master clock configuration for Sm, Fm, and Fm+ are described in 13.22.6.2.4.1.1 Clock Generation (Standard-Mode, Fast-Mode, and Fast-Mode Plus). For Hs, refer to 13.22.6.2.4.1.2 Master Clock Generation (High-Speed Mode).

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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