14.1.3.3 SRAM Access Mode

The SRAM access mode is used to read and write AT86RF212B frame buffer beginning with a specified byte address. It enables to access dedicated buffer data directly from a desired address without a need of incrementing the frame buffer from the top.

The SRAM access mode allows accessing dedicated bytes within the Frame Buffer or AES address space. This may reduce the SPI traffic.

During frame receive, after occurrence of IRQ_2 (RX_START), an SRAM access can be used to upload the PHR field while preserving Dynamic Frame Buffer Protection.

Each SRAM access starts with /SEL = L. The first transferred byte on MOSI shall be the command byte and must indicate an SRAM access mode according to the definition in SPI Command Byte Definition table. The following byte indicates the start address of the write or read access.

SRAM address space:

Frame Buffer: 0x00 to 0x7F
AES: 0x82 to 0x94

On SRAM read access, one or more bytes of read data are transferred on MISO starting with the third byte of the access sequence.

Figure 14-11. Packet Structure – SRAM Read Access

On SRAM write access, one or more bytes of write data are transferred on MOSI starting with the third byte of the access sequence. Do not attempt to read or write bytes beyond the SRAM buffer size.

Figure 14-12. Packet Structure – SRAM Write Access

As long as /SEL = L, every subsequent byte read or byte write increments the address counter of the Frame Buffer until the SRAM access is terminated by /SEL = H.

The figures below illustrate an exemplary SPI sequence of an AT86RF212B SRAM access to read and write a data package of five byte length, respectively.

Figure 14-13. Exemplary SPI Sequence – SRAM Read Access of a 5-byte Data Package

Figure 14-14. Exemplary SPI Sequence – SRAM Write Access of a 5-byte Data Package

Note:

The SRAM access mode is not intended to be used as an alternative to the Frame Buffer access modes.
Frame Buffer access violations are not indicated by a TRX_UR interrupt when using the SRAM access mode.