14.1.3 SPI Protocol
Each SPI sequence starts with transferring a command byte from the SPI master via MOSI with the MSB first. This command byte defines the SPI access mode and additional mode-dependent information.
| Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 | Access Mode | Access Type |
|---|---|---|---|---|---|---|---|---|---|
| 1 | 0 | Register address [5:0] |
Register access
|
Read access | |||||
| 1 | 1 | Register address [5:0] | Write access | ||||||
| 0 | 0 | 1 | Reserved |
Frame Buffer access
|
Read access | ||||
| 0 | 1 | 1 | Reserved | Write access | |||||
| 0 | 0 | 0 | Reserved |
SRAM access
|
Read access | ||||
| 0 | 1 | 0 | Reserved | Write access | |||||
Each SPI transfer returns bytes back to the SPI master on MISO output pin. The content of the first byte (see value PHY_STATUS in the following register-, frame buffer- and SRAM access mode figures) is set to zero after reset. To transfer status information of the radio transceiver to the microcontroller, the content of the first byte can be configured with the SPI_CMD_MODE bits in the TRX_CTRL_1 register (TRX_CTRL_1.SPI_CMD_MODE).
The different access modes are described within the following sections.