13.18.8.7 Channel
This register allows the user to configure channel n. To write to this register, do a single 32-bit write of all the configuration data.
| Name: | CHANNELn |
| Offset: | 0x20 + n*0x04 [n=0..11] |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ONDEMAND | RUNSTDBY | EDGSEL[1:0] | PATH[1:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EVGEN[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bit 15 – ONDEMAND Generic Clock On Demand
This bit is used to determine whether the generic clock is requested.
| Value | Description |
|---|---|
| 0 | Generic clock for a channel is always on, if the channel is configured and generic clock source is enabled. |
| 1 | Generic clock is requested on demand while an event is handled |
Bit 14 – RUNSTDBY Run in Standby
This bit is used to define the behavior during standby sleep mode.
| Value | Description |
|---|---|
| 0 | The channel is disabled in standby sleep mode. |
| 1 | The channel is not stopped in standby sleep mode and depends on the CHANNEL.ONDEMAND. |
Bits 11:10 – EDGSEL[1:0] Edge Detection Selection
These bits set the type of edge detection to be used on the channel.
These bits must be written to zero when using the asynchronous path.
| Value | Name | Description |
|---|---|---|
| 0x0 | NO_EVT_OUTPUT | No event output when using the resynchronized or synchronous path |
| 0x1 | RISING_EDGE | Event detection only on the rising edge of the signal from the event generator |
| 0x2 | FALLING_EDGE | Event detection only on the falling edge of the signal from the event generator |
| 0x3 | BOTH_EDGES | Event detection on rising and falling edges of the signal from the event generator |
Bits 9:8 – PATH[1:0] Path Selection
These bits are used to choose which path will be used by the selected channel.
The path choice can be limited by the channel source; see the table in USERm.
| Value | Name | Description |
|---|---|---|
| 0x0 | SYNCHRONOUS | Synchronous path |
| 0x1 | RESYNCHRONIZED | Resynchronized path |
| 0x2 | ASYNCHRONOUS | Asynchronous path |
| 0x3 | — | Reserved |
Bits 6:0 – EVGEN[6:0] Event Generator
These bits are used to choose the event generator to connect to the selected channel.
| Value | Event Generator | Description |
|---|---|---|
| 0x00 | NONE | No event generator selected |
| 0x01 | RTC CMP0 | Compare 0 (mode 0 and 1) or Alarm 0 (mode 2) |
| 0x02 | RTC CMP1 | Compare 1 |
| 0x03 | RTC OVF | Overflow |
| 0x04 | RTC PER0 | Period 0 |
| 0x05 | RTC PER1 | Period 1 |
| 0x06 | RTC PER2 | Period 2 |
| 0x07 | RTC PER3 | Period 3 |
| 0x08 | RTC PER4 | Period 4 |
| 0x09 | RTC PER5 | Period 5 |
| 0x0A | RTC PER6 | Period 6 |
| 0x0B | RTC PER7 | Period 7 |
| 0x0C | EIC EXTINT0 | External Interrupt 0 |
| 0x0D | EIC EXTINT1 | External Interrupt 1 |
| 0x0E | EIC EXTINT2 | External Interrupt 2 |
| 0x0F | EIC EXTINT3 | External Interrupt 3 |
| 0x10 | EIC EXTINT4 | External Interrupt 4 |
| 0x11 | EIC EXTINT5 | External Interrupt 5 |
| 0x12 | EIC EXTINT6 | External Interrupt 6 |
| 0x13 | EIC EXTINT7 | External Interrupt 7 |
| 0x14 | EIC EXTINT8 | External Interrupt 8 |
| 0x15 | EIC EXTINT9 | External Interrupt 9 |
| 0x16 | EIC EXTINT10 | External Interrupt 10 |
| 0x17 | EIC EXTINT11 | External Interrupt 11 |
| 0x18 | EIC EXTINT12 | External Interrupt 12 |
| 0x19 | EIC EXTINT13 | External Interrupt 13 |
| 0x1A | EIC EXTINT14 | External Interrupt 14 |
| 0x1B | EIC EXTINT15 | External Interrupt 15 |
| 0x1C | DMAC CH0 | Channel 0 |
| 0x1D | DMAC CH1 | Channel 1 |
| 0x1E | DMAC CH2 | Channel 2 |
| 0x1F | DMAC CH3 | Channel 3 |
| 0x20 | DMAC CH4 | Channel 4 |
| 0x21 | DMAC CH5 | Channel 5 |
| 0x22 | DMAC CH6 | Channel 6 |
| 0x23 | DMAC CH7 | Channel 7 |
| 0x24 | TCC0 OVF | Overflow |
| 0x25 | TCC0 TRG | Trig |
| 0x26 | TCC0 CNT | Counter |
| 0x27 | TCC0_MCX0 | Match/Capture 0 |
| 0x28 | TCC0_MCX1 | Match/Capture 1 |
| 0x29 | TCC0_MCX2 | Match/Capture 2 |
| 0x2A | TCC0_MCX3 | Match/Capture 3 |
| 0x2B | TCC1 OVF | Overflow |
| 0x2C | TCC1 TRG | Trig |
| 0x2D | TCC1 CNT | Counter |
| 0x2E | TCC1_MCX0 | Match/Capture 0 |
| 0x2F | TCC1_MCX1 | Match/Capture 1 |
| 0x30 | TCC2 OVF | Overflow |
| 0x31 | TCC2 TRG | Trig |
| 0x32 | TCC2 CNT | Counter |
| 0x33 | TCC2_MCX0 | Match/Capture 0 |
| 0x34 | TCC2_MCX1 | Match/Capture 1 |
| 0x35 | TC0 OVF | Overflow/Underflow |
| 0x36 | TC0 MC0 | Match/Capture 0 |
| 0x37 | TC0 MC1 | Match/Capture 1 |
| 0x38 | TC1 OVF | Overflow/Underflow |
| 0x39 | TC1 MC0 | Match/Capture 0 |
| 0x3A | TC1 MC1 | Match/Capture 1 |
| 0x3B | Reserved | Reserved |
| 0x3C | Reserved | Reserved |
| 0x3D | Reserved | Reserved |
| 0x3E | Reserved | Reserved |
| 0x3F | Reserved | Reserved |
| 0x40 | Reserved | Reserved |
| 0x41 | TC4 OVF | Overflow/Underflow |
| 0x42 | TC4 MC0 | Match/Capture 0 |
| 0x43 | TC4 MC1 | Match/Capture 1 |
| 0x44 | ADC RESRDY | Result Ready |
| 0x45 | ADC WINMON | Window Monitor |
| 0x46 | AC COMP0 | Comparator 0 |
| 0x47 | AC COMP1 | Comparator 1 |
| 0x48 | AC WIN0 | Window 0 |
| 0x49 | Reserved | Reserved |
| 0x4A | Reserved | Reserved |
| 0x4B | PTC EOC | End of Conversion |
| 0x4C | PTC WCOMP | Window Comparator |
| 0x4D | Reserved | Reserved |
| 0x4E | CCL LUTOUT0 | CCL output |
| 0x4F | CCL LUTOUT1 | CCL output |
| 0x50 | CCL LUTOUT2 | CCL output |
| 0x51 | CCL LUTOUT3 | CCL output |
| 0x52 | PAC ACCERR | Access Error |
| 0x53-0x7F | Reserved | — |