13.18.8.5 Interrupt Flag Status and Clear

Name: INTFLAG
Offset: 0x18
Reset: 0x00000000
Property: 

Bit 3130292827262524 
     EVD11EVD10EVD9EVD8 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 2322212019181716 
 EVD7EVD6EVD5EVD4EVD3EVD2EVD1EVD0 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
     OVR11OVR10OVR9OVR8 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
 OVR7OVR6OVR5OVR4OVR3OVR2OVR1OVR0 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27 – EVDn Event Detected Channel n [n=11..0]

This flag is set on the next CLK_EVSYS_APB cycle when an event is being propagated through the channel, and an interrupt request will be generated if INTENCLR/SET.EVDn is '1'.

When the event channel path is asynchronous, the EVDn interrupt flag will not be set.

Writing '0' to this bit has no effect.

Writing '1' to this bit will clear the Event Detected Channel n interrupt flag.

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 – OVRn Overrun Channel n [n=11..0]

This flag is set on the next CLK_EVSYS_APB cycle when an event is being propagated through the channel, and an interrupt request will be generated if INTENCLR/SET.OVRn is '1'.

When the event channel path is asynchronous, the OVRn interrupt flag will not be set.

Writing '0' to this bit has no effect.

Writing '1' to this bit will clear the Overrun Detected Channel n interrupt flag.