13.24.8.20 Waveform Buffer

Name: WAVEBUF
Offset: 0x68
Reset: 0x00000000
Property: Write-Synchronized, Read-Synchronized

Bit 3130292827262524 
     SWAPB 3SWAPB 2SWAPB 1SWAPB 0 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
     CICCENB3CICCENB2CICCENB1CICCENB0 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
 CIPERENB RAMPB[1:0] WAVEGENB[2:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bits 24, 25, 26, 27 – SWAPB  Swap DTI output pair x Buffer

These register bits are the buffer bits for the SWAP register bits. If double buffering is used, valid content in these bits is copied to the corresponding SWAPx bits on an UPDATE condition.

Bits 8, 9, 10, 11 – CICCENB Circular CCx Buffer Enable

These register bits are the buffer bits for CICCENx register bits. If double buffering is used, valid content in these bits is copied to the corresponding CICCENx bits on a UPDATE condition.

Bit 7 – CIPERENB Circular Period Enable Buffer

This register bit is the buffer bit for CIPEREN register bit. If double buffering is used, valid content in this bit is copied to the corresponding CIPEREN bit on a UPDATE condition.

Bits 5:4 – RAMPB[1:0] Ramp Operation Buffer

These register bits are the buffer bits for RAMP register bits. If double buffering is used, valid content in these bits is copied to the corresponding RAMP bits on a UPDATE condition.

Bits 2:0 – WAVEGENB[2:0] Waveform Generation Operation Buffer

These register bits are the buffer bits for WAVEGEN register bits. If double buffering is used, valid content in these bits is copied to the corresponding WAVEGEN bits on a UPDATE condition.