13.24.8.14 Counter Value

Note: Prior to any read access, this register must be synchronized by user by writing the according TCC Command value to the Control B Set register (CTRLBSET.CMD=READSYNC).
Name: COUNT
Offset: 0x34
Reset: 0x00000000
Property: PAC Write-Protection, Write-Synchronized, Read-Synchronized

Bit 3130292827262524 
 COUNT[31:24] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
 COUNT[23:16] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 COUNT[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 COUNT[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 31:0 – COUNT[31:0] Counter Value

These bits hold the value of the counter register.

Note: When the TCC is configured as 24- or 16-bit timer/counter, the excess bits are read zero.
Note: This bit field occupies the MSB of the register, [31:m]. m is dependent on the Resolution bit in the Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION Bits [31:m]
0x0 - NONE 31:0 (depicted)
0x1 - DITH4 31:4
0x2 - DITH5 31:5
0x3 - DITH6 31:6