13.24.8.16 Waveform

Name: WAVE
Offset: 0x3C
Reset: 0x00000000
Property: Write-Synchronized

Bit 3130292827262524 
     SWAP3SWAP2SWAP1SWAP0 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 2322212019181716 
     POL3POL2POL1POL0 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 15141312111098 
     CICCEN3CICCEN2CICCEN1CICCEN0 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
 CIPEREN RAMP[1:0] WAVEGEN[2:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bits 24, 25, 26, 27 – SWAP Swap DTI Output Pair x

Setting these bits enables output swap of DTI outputs [x] and [x+WO_NUM/2]. Note the DTIxEN settings will not affect the swap operation.

Bits 16, 17, 18, 19 – POL Channel Polarity x

Setting these bits enables the output polarity in single-slope and dual-slope PWM operations.

ValueNameDescription
0 (single-slope PWM waveform generation) Compare output is initialized to ~DIR and set to DIR when TCC counter matches CCx value
1 (single-slope PWM waveform generation) Compare output is initialized to DIR and set to ~DIR when TCC counter matches CCx value.
0 (dual-slope PWM waveform generation) Compare output is set to ~DIR when TCC counter matches CCx value
1 (dual-slope PWM waveform generation) Compare output is set to DIR when TCC counter matches CCx value.

Bits 8, 9, 10, 11 – CICCEN Circular CC Enable x

Setting this bits enables the compare circular buffer option on channel. When the bit is set, CCx register value is copied-back into the CCx register on UPDATE condition.

Bit 7 – CIPEREN Circular Period Enable

Setting this bits enable the period circular buffer option. When the bit is set, the PER register value is copied-back into the PERB register on UPDATE condition.

Bits 5:4 – RAMP[1:0] Ramp Operation

These bits select Ramp operation (RAMP). These bits are not synchronized.

ValueNameDescription
0x0 RAMP1 RAMP1 operation
0x1 RAMP2A Alternative RAMP2 operation
0x2 RAMP2 RAMP2 operation
0x3 RAMP2C Critical RAMP2 operation

Bits 2:0 – WAVEGEN[2:0] Waveform Generation Operation

These bits select the waveform generation operation. The settings impact the top value and control if frequency or PWM waveform generation should be used. These bits are not synchronized.

Value Name Description
Operation Top Update Waveform Output

On Match

Waveform Output

On Update

OVFIF/Event

Up Down

0x0 NFRQ Normal Frequency PER TOP/Zero Toggle Stable TOP Zero
0x1 MFRQ Match Frequency CC0 TOP/Zero Toggle Stable TOP Zero
0x2 NPWM Normal PWM PER TOP/Zero Set Clear TOP Zero
0x3 Reserved
0x4 DSCRITICAL Dual-slope PWM PER Zero ~DIR Stable Zero
0x5 DSBOTTOM Dual-slope PWM PER Zero ~DIR Stable Zero
0x6 DSBOTH Dual-slope PWM PER TOP & Zero ~DIR Stable TOP Zero
0x7 DSTOP Dual-slope PWM PER Zero ~DIR Stable TOP