13.8.8.7 Standby Configuration

Name: STDBYCFG
Offset: 0x08
Reset: 0x0000
Property: PAC Write-Protection

Bit 15141312111098 
   BBIASLP[1:0]BBIASHS[1:0]LINKPD[1:0] 
Access R/WR/WRRR/WR/W 
Reset 000000 
Bit 76543210 
 VREGSMOD[1:0]DPGPD1DPGPD0  PDCFG[1:0] 
Access RRR/WR/WR/WR/W 
Reset 000000 

Bits 13:12 – BBIASLP[1:0] Back Bias for HMCRAMCLP

Refer to Table 13-25 for details.

ValueDescription
0Retention Back Biasing mode
1Standby Back Biasing mode
2Standby OFF mode
3Always OFF mode

Bits 11:10 – BBIASHS[1:0] Back Bias for HMCRAMCHS

Refer to Table 13-25 for details.

ValueDescription
0Retention Back Biasing mode
1Standby Back Biasing mode
2Standby OFF mode
3Always OFF mode

Bits 9:8 – LINKPD[1:0] Linked Power Domain

Refer to 13.8.6.4.2 Linked Power Domains for details.

ValueNameDescription
0x0DEFAULTPower domains PD0/PD1/PD2 are not linked.
0x1PD01

Power domains PD0 and PD1 are linked.

If PD0 is active, then PD1 is active even if there is no activity in PD1

.
0x2PD12

Power domains PD1 and PD2 are linked.

If PD1 is active, then PD2 is active even if there is no activity in PD2.

0x3PD012

All Power domains are linked.

If PD0 is active, then PD1 and PD2 are active even if there is no activity in PD1 or PD2.

Bit 5 – DPGPD1 Dynamic Power Gating for Power Domain 1

ValueDescription
0Dynamic SleepWalking for power domain 1 is disabled.
1Dynamic SleepWalking for power domain 1 is enabled.

Bit 4 – DPGPD0 Dynamic Power Gating for Power Domain 0

ValueDescription
0Dynamic SleepWalking for power domain 0 is disabled.
1Dynamic SleepWalking for power domain 0 is enabled.

Bits 1:0 – PDCFG[1:0] Power Domain Configuration

ValueNameDescription
0x0DEFAULTIn standby mode, all power domain switching are handled by hardware.
0x1PD0In standby mode, power domain 0 (PD0) is forced ACTIVE. Other power domain switching is handled by hardware.
0x2PD01In standby mode, power domains PD0 and PD1 are forced ACTIVE. Power domain 2 switching is handled by hardware.
0x3PD012In standby mode, all power domains are forced ACTIVE.