14.6.1.1 Overview

The security module is based on an AES-128 core according to FIPS197 standard, refer to [10]. The security module works independently of other building blocks of the AT86RF212B. Encryption and decryption can be performed in parallel with a frame transmission or reception.

The control of the security block is implemented as an SRAM access to address space 0x82 to 0x94. A Fast SRAM access mode allows for simultaneous new data writes and reads of processed data within the same SPI transfer. This access procedure is used to reduce the turnaround time for ECB and CBC modes.

In addition, the security module contains another 128-bit register to store the initial key used for security operations. This initial key is not modified by the security module.