14.6.1.5 Data Transfer – Fast SRAM Access

The ECB and CBC modules including the AES core are clocked with 16MHz. One AES operation takes t_AES = 23.4µs to execute. That means that the processing of the data is usually faster than the transfer of the data via the SPI interface.

To reduce the overall processing time, the AT86RF212B provides a Fast SRAM access for the address space 0x82 to 0x94.

Figure 14-61. Packet Structure – Fast SRAM Access Mode

Note: Byte 19 is the mirrored version of register AES_CTRL on SRAM address 0x94, see register description AES_CTRL_MIRROR for details.

In contrast to a standard SRAM access, the Fast SRAM access allows writing and reading of data simultaneously during one SPI access for consecutive AES operations (AES run).

For each byte P0 transferred to pin 22 (MOSI) for example in “AES access #1”, see the figure above (lower part), the previous content of the respective AES register C0 is clocked out at pin 20 (MISO) with an offset of one byte.

In the example shown in the above figure the initial plaintext P0 – P15 is written to the SRAM within “AES access #0”. The last command on address 0x94 (AES_CTRL_MIRROR) starts the AES operation (“AES run #0”). In the next “AES access #1” new plaintext data P0 – P15 is written to the SRAM for the second AES run, in parallel the ciphertext C0 – C15 from the first AES run is clocked out at pin MISO. To read the ciphertext from the last “AES run #(n)” one dummy “AES access #(n+1)” is needed.

Note: The SRAM write access always overwrites the previous processing result.

The Fast SRAM access automatically applies to all write operations to SRAM addresses 0x82 to 0x94.