58.6.7 Inter-IC Sound Multi-Channel Controller (I2SMCC)

Timings are given in the following domains:

1.8V domain: VDDIO from 1.7V to 1.95V, maximum external capacitor = 15 pF, DRV = 1, SR = 1
3.3V domain: VDDIO from 3.00V to 3.6V, maximum external capacitor = 15 pF, DRV = 0, SR = 1

Figure 58-29. I2SMCC Timing Diagram in Host Mode

Figure 58-30. I2SMCC Timing Diagram in Client Mode

Table 58-33. I2SMCC Timings⁽¹⁾
Symbol	Parameter	Conditions	Min	Max	Unit
Host Mode
I2S₀	I2SMCC_DINx setup time before I2SMCC_SCK rises	3.3V domain	10.5	–	ns
I2S₀	I2SMCC_DINx setup time before I2SMCC_SCK rises	1.8V domain	12.7	–	ns
I2S₁	I2SMCC_DINx hold time after I2SMCC_SCK rises	3.3V domain	0	–	ns
I2S₁	I2SMCC_DINx hold time after I2SMCC_SCK rises	1.8V domain	0	–	ns
I2S₂	I2SMCC_SCK falling to I2SMCC_DOUTx delay	3.3V domain	0	3.4	ns
I2S₂	I2SMCC_SCK falling to I2SMCC_DOUTx delay	1.8V domain	0	1.7	ns
I2S₃	I2SMCC_SCK falling to I2SMCC_WS delay	3.3V domain	0	3.5	ns
I2S₃	I2SMCC_SCK falling to I2SMCC_WS delay	1.8V domain	0	1.9	ns
Client Mode
I2S₄	I2SMCC_DINx setup time before I2SMCC_SCK rises	3.3V domain	0.1	–	ns
I2S₄	I2SMCC_DINx setup time before I2SMCC_SCK rises	1.8V domain	0.2	–	ns
I2S₅	I2SMCC_DINx hold time after I2SMCC_SCK rises	3.3V domain	2.1	–	ns
I2S₅	I2SMCC_DINx hold time after I2SMCC_SCK rises	1.8V domain	2.3	–	ns
I2S₆	I2SMCC_WS setup time before I2SMCC_SCK rises	3.3V domain	2.2	–	ns
I2S₆	I2SMCC_WS setup time before I2SMCC_SCK rises	1.8V domain	2.5	–	ns
I2S₇	I2SMCC_WS hold time after I2SMCC_SCK rises	3.3V domain	1.3	–	ns
I2S₇	I2SMCC_WS hold time after I2SMCC_SCK rises	1.8V domain	1.4	–	ns
I2S₈	I2SMCC_SCK falling to I2SMCC_DOUTx delay	3.3V domain	1.9	12.0	ns
I2S₈	I2SMCC_SCK falling to I2SMCC_DOUTx delay	1.8V domain	2.5	12.7	ns

Note: