58.6.6 Synchronous Serial Controller (SSC)

Timings are given in the following domains:

1.8V domain: VDDIO from 1.7V to 1.95V, maximum external capacitor = 15 pF, DRV = 1, SR = 1
3.3V domain: VDDIO from 3.00V to 3.6V, maximum external capacitor = 15 pF, DRV = 0, SR = 1

Figure 58-21. SSC Transmitter, TK and TF in Output

Figure 58-22. SSC Transmitter, TK in Input and TF in Output

Figure 58-23. SSC Transmitter, TK in Output and TF in Input

Figure 58-24. SSC Transmitter, TK and TF in Input

Figure 58-25. SSC Receiver RK and RF in Input

Figure 58-26. SSC Receiver, RK in Input and RF in Output

Figure 58-27. SSC Receiver, RK and RF in Output

Figure 58-28. SSC Receiver, RK in Output and RF in Input

Table 58-32. SSC Timings⁽²⁾
Symbol	Power supply	Conditions	1.8V		3.3V		Unit
Symbol	Parameter	Conditions	Min	Max	Min	Max	Unit
Transmitter
SSC₀	TK edge to TF/TD (TK output, TF output)	–	0	3.8	0	5.5	ns
SSC₁	TK edge to TF/TD (TK input, TF output)	–	3.1	14.4	2.5	13.8	ns
SSC₂	TF setup time before TK edge (TK output)	–	12.8	–	12.3	–	ns
SSC₃	TF hold time after TK edge (TK output)	–	0	–	0	–	ns
SSC₄	TK edge to TF/TD (TK output, TF input)	–	0	3.8	0	5.5	ns
SSC₄	TK edge to TF/TD (TK output, TF input)	STTDLY = 0 START = 4, 5 or 7	2 × t_CPMCK	3.8 + (2 × t_CPMCK)	2 × t_CPMCK	5.5 + (2 × t_CPMCK)	ns
SSC₅	TF setup time before TK edge (TK input)	–	0	–	0	–	ns
SSC₆	TF hold time after TK edge (TK input)	–	t_CPMCK	–	t_CPMCK	–	ns
SSC₇	TK edge to TF/TD (TK input, TF input)	–	3.1	14.3	2.5	13.8	ns
SSC₇	TK edge to TF/TD (TK input, TF input)	STTDLY = 0 START = 4, 5 or 7	3.1 + (3 × t_CPMCK)	14.3 + (3 × t_CPMCK)	2.5 + (3 × t_CPMCK)	13.8 + (3 × t_CPMCK)	ns
SSC₁₄	TK low or high time⁽¹⁾	V_TK > V_IH or V_TK < V_IL	3 x t_CPMCK + 1.5	–	3 x t_CPMCK + 1.7	–	ns
SSC₁₅	TK rise time or fall time⁽¹⁾	10% to 90%	–	10	–	10	ns
Receiver
SSC₈	RF/RD setup time before RK edge (RK input)	–	0	–	0	–	ns
SSC₉	RF/RD hold time after RK edge (RK input)	–	t_CPMCK	–	t_CPMCK	–	ns
SSC₁₀	RK edge to RF (RK input)	–	3.5	15.8	3.0	15.2	ns
SSC₁₁	RF/RD setup time before RK edge (RK output)	–	13.3 - t_CPMCK	–	12.8 - t_CPMCK	–	ns
SSC₁₂	RF/RD hold time after RK edge (RK output)	–	t_CPMCK	–	t_CPMCK	–	ns
SSC₁₃	RK edge to RF (RK output)	–	0	4.9	0	6.5	ns

Note:

SSC₁₄ and SSC₁₅ apply to RK when RK is selected instead of TK (SSC_TCMR.CKS = RK).
The data provided in this table are extracted from circuit simulation results.