58.6.8 Image Sensor Interface (ISI)

Timings are given in the following domains:
  • 1.8V domain: VDDIO from 1.7V to 1.95V, maximum external capacitor = 15 pF, DRV = 1, SR = 1
  • 3.3V domain: VDDIO from 3.00V to 3.6V, maximum external capacitor = 15 pF, DRV = 0, SR = 1
Figure 58-31. ISI Timing Diagram

Table 58-34. ISI Timings(1)
SymbolParameterConditionsMinMaxUnit
ISI1DATA setup time before PIXCLK rises3.3V domain2.5–ns
1.8V domain2.8–ns
ISI2DATA hold time after PIXCLK rises3.3V domain0–ns
1.8V domain0–ns
ISI3VSYNC / HSYNC / FIELD setup time before PIXCLK rises3.3V domain2.5–ns
1.8V domain2.8–ns
ISI4VSYNC / HSYNC / FIELD hold time after PIXCLK rises3.3V domain0–ns
1.8V domain0–ns
ISI5PIXCLK frequency3.3V domain–75MHz
1.8V domain–75MHz
Note:
  1. The data provided in this table are extracted from circuit simulation results.