33.7.15 SDRAMC Write Protection Status Register


Bit	31	30	29	28	27	26	25	24
	ECLASS					SWETYP[2:0]
Access	R					R	R	R
Reset	0					0	0	0


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
	WPVSRC[7:0]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
					SWE	SEQE	CGD	WPEN
Access					R	R	R	R
Reset					0	0	0	0

Bit 31 – ECLASS Software Error Class (cleared on read)

Value	Name	Description
0	WARNING	An abnormal access is performed but it does not affect system functionality.
1	ERROR	An access is performed into some registers after memory device initialization sequence.

Bits 26:24 – SWETYP[2:0] Software Error Type (cleared on read)

Value	Name	Description
0	READ_WO	A write-only register has been read (Warning).
1	WRITE_RO	A write access has been performed on a read-only register (Warning).
2	UNDEF_RW	Access to an undefined address (Warning).
3	W_AFTER_INIT	Write access performed into some configuration registers after memory device initialization, i.e. if SDRAMC_TR.COUNT > 0 (Error).

Bits 15:8 – WPVSRC[7:0] Write Protection Violation Source

When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.

When WPVS=0 and SWE=1, WPVSRC reports the address of the incorrect software access. As soon as WPVS=1, WPVSRC returns the address of the write-protected violation.

Bit 3 – SWE Software Control Error (cleared on read)

Value	Description
0	No software error has occurred since the last read of SDRAMC_WPSR.
1	A software error has occurred since the last read of SDRAMC_WPSR. The field SWETYP details the type of software error; the associated incorrect software access is reported in the field WPVSRC (if WPVS=0).

Bit 2 – SEQE Internal Sequencer Error (cleared on read)

Value	Description
0	No peripheral internal sequencer error has occurred since the last read of SDRAMC_WPSR.
1	A peripheral internal sequencer error has occurred since the last read of SDRAMC_WPSR. This flag can only be set under abnormal operating conditions.

Bit 1 – CGD Clock Glitch Detected (cleared on read)

Value	Description
0	The clock monitoring circuitry has not been corrupted since the last read of SDRAMC_WPSR. Under normal operating conditions, this bit is always cleared.
1	The clock monitoring circuitry has been corrupted since the last read of SDRAMC_WPSR. This flag can only be set in case of an abnormal clock signal waveform (glitch).

Bit 0 – WPEN Write Protection Violation Status

Value	Description
0	No write protection violation has occurred since the last read of the QSPI_WPSR.
1	A write protection violation has occurred since the last read of the QSPI_WPSR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC.

Name:	SDRAMC_WPSR
Offset:	0x40
Reset:	0x00000000
Property:	Read-only