31.5.3.6 Multi-Port DDR and SDRAM Controllers

The product embeds a multi-port DDR Controller. This allows to use three additional ports on the MPDDRC to lessen the EBI load from a part of SDRAM accesses. This increases the bandwidth when DDR2 and NAND Flash devices are used. This feature is used with DDR2, LPDDR1 and SDR-SDRAM devices in Address/data or Address/data/command multiplexed mode.

It is controlled by the DDR_MP_EN bit in EBI Chip Select Assignment Register.

Figure 31-4. Multi-Port Enabled MPDDRC (DDR_MP_EN = 1)
When:
  • a NAND Flash memory is connected to D[23:16] and
  • a DDR2-SDRAM or LPDDR-SDRAM is connected to D[15:0],

the bits SFR_CCFG_EBICSA.DDR_MP_EN and SFR_CCFG_EBICSA.NFD0_ON_D16 must both be set before performing the SDRAM initialization.

Figure 31-5. Multi-Port Disabled MPDDRC (DDR_MP_EN = 0)

Set DQIEN_F to 1: force EBI D0-D15 data pads in Input mode. Mandatory when EBI D[15:0] is shared between DDR-DRAM (LPDDR/DDR2) and static memory (via MPDDRC and SMC).

Figure 31-6. Multi-Port Disabled SDRAMC (DDR_MP_EN = 0)
Figure 31-7. Multiplexed Mode Multi-Port Enabled SDRAMC (DDR_MP_EN = 1) (With Addr/Data/Cmd Multiplexed Mode)

The product embeds a multi-port SDR Controller in Address/Data or Address/Data/Command multiplexed mode. This allows to use three additional ports on the SDRAMC to remove SDRAM accesses from the EBI load. This increases the bandwidth when SDR-SDRAM and a full SMC are used. This configuration allows to support up to five chip selects on SMC.