22.5.1.2.3 PDPLL - Power Domain of FPDLL96M, DFLL48M and DFLLULP

PDPLL is the FPDLL96M, DFLL48M and DFLLULP clock sources power domain.

In standby sleep mode, it can be turned off to save leakage consumption according to user configuration.

Depending on peripheral settings, the FDPLL96M and DFLL48M can also be switched off if no clock activity is required.