30.6.1 Control A

Name:	CTRLA
Offset:	0x000
Reset:	0x00
Property:	PAC Write Protection, Enable-Protected Bits, Write-Synchronized Bits


Bit	7	6	5	4	3	2	1	0
	SILACC	DRP		TAMPERS			ENABLE	SWRST
Access	R/W	R/W		R/W			R/W	R/W
Reset	0	0		0			0	0

Bit 7 – SILACC Silent Access

Enables differential storage of data.

Note: This bit is enable-protected. This bit is not synchronized.

Value	Description
0	Silent access is disabled.
1	Silent access is enabled.

Bit 6 – DRP Data Remanence Prevention

Enables periodic Data Remanence Prevention in TrustRAM.

Note: This bit is enable-protected. This bit is not synchronized.

Value	Description
0	Data remanence prevention is disabled.
1	Data remanence prevention is enabled.

Bit 4 – TAMPERS Tamper Erase

Auto-erases TrustRAM and DSCC.DSCKEY on tamper event.

Note: This bit is enable-protected. This bit is not synchronized.

Value	Description
0	Tamper erase is disabled.
1	Tamper erase is enabled.

Bit 1 – ENABLE Enable

Note:

This bit is write-synchronized: SYNCBUSY.ENABLE must be checked to ensure the CTRLA.ENABLE synchronization is complete.
This bit is not enable-protected.

Value	Description
0	The TRAM is disabled.
1	The TRAM is enabled.

Bit 0 – SWRST Software Reset

Writing a zero to this bit has no effect.

Writing a one to this bit resets all registers in the TRAM to their initial state, and the TRAM will be disabled. This bit can also be set via hardware when a tamper occurs while CTRLA.TAMPERS is set.

Writing a one to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write operation will be discarded.

Note:

When the CTRLA.SWRST is written, the user must poll SYNCBUSY.SWRST bit to know when the reset operation is complete.
During a SWRST, access to registers/bits without SWRST are disallowed until SYNCBUSY.SWRST is cleared by hardware.
This bit is not enable protected.

Value	Description
0	There is no reset operation ongoing.
1	The reset operation is ongoing.