30.6 Register Summary
Refer to the Registers Description section for more details on register properties and access permissions.
| Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 | CTRLA | 7:0 | SILACC | DRP | TAMPERS | ENABLE | SWRST | |||
0x01 ... 0x03 | Reserved | |||||||||
| 0x04 | INTENCLR | 7:0 | DRP | ERR | ||||||
| 0x05 | INTENSET | 7:0 | DRP | ERR | ||||||
| 0x06 | INTFLAG | 7:0 | DRP | ERR | ||||||
| 0x07 | STATUS | 7:0 | DRP | RAMINV | ||||||
| 0x08 | SYNCBUSY | 31:24 | ||||||||
| 23:16 | ||||||||||
| 15:8 | ||||||||||
| 7:0 | ENABLE | SWRST | ||||||||
| 0x0C | DSCC | 31:24 | DSCEN | DSCKEY[29:24] | ||||||
| 23:16 | DSCKEY[23:16] | |||||||||
| 15:8 | DSCKEY[15:8] | |||||||||
| 7:0 | DSCKEY[7:0] | |||||||||
0x10 ... 0x01FF | Reserved | |||||||||
| 0x0200 | RAM0 | 31:24 | DATA[31:24] | |||||||
| 23:16 | DATA[23:16] | |||||||||
| 15:8 | DATA[15:8] | |||||||||
| 7:0 | DATA[7:0] | |||||||||
| ... | ||||||||||
| 0x03FC | RAM127 | 31:24 | DATA[31:24] | |||||||
| 23:16 | DATA[23:16] | |||||||||
| 15:8 | DATA[15:8] | |||||||||
| 7:0 | DATA[7:0] | |||||||||