19.7.4 Status
| Name: | STATUS |
| Offset: | 0x0C |
| Reset: | 0x00000000 |
| Property: | – |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ULP32KSW | CLKSW | CLKFAIL | XOSC32KRDY | ||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 4 – ULP32KSW OSCULP32K Clock Switch
| Value | Description |
|---|---|
| 0 | CLK_ULP32K clock switch to CLK_XOSC32K is not complete. |
| 1 | CLK_ULP32K clock switch to CLK_XOSC32K is complete. |
Bit 3 – CLKSW XOSC32K Clock Switch
| Value | Description |
|---|---|
| 0 | CLK_XOSC32K clock switch to CLK_ULP32K clock is not complete. |
| 1 | CLK_XOSC32K clock switch to CLK_ULP32K clock is complete. |
Bit 2 – CLKFAIL XOSC32K Clock Failure Detector
| Value | Description |
|---|---|
| 0 | No XOSC32K failure is detected. |
| 1 | An XOSC32K failure is detected. |
Bit 0 – XOSC32KRDY XOSC32K Ready
| Value | Description |
|---|---|
| 0 | XOSC32K is not ready. |
| 1 | XOSC32K is stable and ready to be used as a clock source. |