35.7.2 Control B

Name: CTRLB
Offset: 0x04
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected Bits, Write-Synchronized Bits

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
 FIFOCLR[1:0]    RXEN  
Access R/WR/WR/W 
Reset 000 
Bit 15141312111098 
 AMODE[1:0]MSSEN   SSDE  
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
  PLOADEN   CHSIZE[2:0] 
Access R/WR/WR/WR/W 
Reset 0000 

Bits 23:22 – FIFOCLR[1:0] FIFO Clear

Note: This bit field is write-synchronized: SYNCBUSY.CTRLB must be checked to ensure the CTRLB.FIFOCLR synchronization is complete.
Note: This bit field is not enable-protected.
ValueNameDescription
0x0NONENo action
0x1TXFIFOClear TX FIFO
0x2RXFIFOClear RX FIFO
0x3BOTHClear both TX/RX FIFO

Bit 17 – RXEN Receiver Enable

Writing '0' to this bit will disable the SPI receiver immediately. The receive buffer will be flushed, data from ongoing receptions will be lost and STATUS.BUFOVF will be cleared.

Writing '1' to this bit when the SPI is disabled will set CTRLB.RXEN immediately. When the SPI is enabled, CTRLB.RXEN is cleared and the receiver enable is only effective at the end of the SYNCBUSY.CTRLB synchronization.

Writing '1' to this bit when the SPI is enabled requires to wait the end of the SYNCBUSY.CTRLB synchronization to ensure the receiver is enabled.

Note: This bit is write-synchronized: SYNCBUSY.CTRLB must be checked to ensure the CTRLB.RXEN synchronization is complete.
Note: This bit is not enable-protected.
ValueDescription
0The receiver is disabled or being enabled.
1The receiver is enabled or it will be enabled when SPI is enabled.

Bits 15:14 – AMODE[1:0] Address Mode

These bits set the Client Addressing mode when the frame format (CTRLA.FORM) with address is used. They are unused in Host mode.

Note: This bit field is enable-protected. This bit field is not synchronized.
ValueNameDescription
0x0MASKADDRMASK is used as a mask to the ADDR register
0x12ADDRSThe client responds to the two unique addresses in ADDR and ADDRMASK
0x2RANGEThe client responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit
0x3-Reserved

Bit 13 – MSSEN Host SPI Select Enable

This bit enables hardware SPI Select (SS) control.

Note: This bit is enable-protected. This bit is not synchronized.
ValueDescription
0Hardware SS control is disabled.
1Hardware SS control is enabled.

Bit 9 – SSDE SPI Select Low Detect Enable

This bit enables wake-up when the SPI Select (SS) pin transitions from high to low.

Note: This bit is enable-protected. This bit is not synchronized.
ValueDescription
0SS low detector is disabled.
1SS low detector is enabled.

Bit 6 – PLOADEN Client Data Preload Enable

Setting this bit will enable preloading of the Client Shift register when there is no transfer in progress. If the SS line is high when DATA is written, it will be transferred immediately to the Shift register.

Note: This bit is enable-protected. This bit is not synchronized.

Bits 2:0 – CHSIZE[2:0] Character Size

Note: This bit field is enable-protected. This bit field is not synchronized.
ValueNameDescription
0x08BIT8 bits
0x19BIT9 bits
0x2-0x7-Reserved