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Arm® Arm926EJ-S™ Processor-Based MPU, 800 MHz, MIPI DSI® or CSI-2, LVDS, RGB, 2D Graphics, Gigabit Ethernet with TSN, CAN-FD, Octal/Quad SPI, Crypto, PUF
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5
Image Subsystem
5.5
Display Serial Interface (DSI)
5.5.6
Functional Description
5.5.6.5
Transmission of Commands
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
4
System Controller
5
Image Subsystem
5.1
Overview
5.2
LCD Controller (LCDC)
5.3
Low Voltage Differential Signaling Controller (LVDSC)
5.4
2D Graphics Engine (GFX2D)
5.5
Display Serial Interface (DSI)
5.5.1
Description
5.5.2
Embedded Characteristics
5.5.3
Block Diagram
5.5.4
I/O Lines Description
5.5.5
Product Dependencies
5.5.6
Functional Description
5.5.6.1
D-PHY Operating Modes
5.5.6.2
D-PHY Control Operation
5.5.6.3
Input Video Interface
5.5.6.4
Generic Interface
5.5.6.5
Transmission of Commands
5.5.6.5.1
Transmission of Commands in Video Mode
5.5.6.5.2
Transmission of Commands in Low-Power
5.5.6.5.3
Transmission of Commands in High-Speed
5.5.6.5.4
Read Command Transmission
5.5.6.5.5
Clock Lane in Low-Power Mode
5.5.6.6
Video Mode Pattern Generator
5.5.6.7
Error Handling
5.5
Register Summary
5.6
Camera Serial Interface (CSI)
5.7
CSI-2 Demultiplexer Controller (CSI2DC)
5.8
Image Sensor Controller (ISC)
6
Audio Subsystem
7
Security and Cryptography Subsystem
8
Connectivity Subsystem
9
USB Subsystem
10
Electrical and Mechanical Characteristics
11
Revision History
Microchip Information
5.5.6.5 Transmission of Commands
