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Arm® Arm926EJ-S™ Processor-Based MPU, 800 MHz, MIPI DSI® or CSI-2, LVDS, RGB, 2D Graphics, Gigabit Ethernet with TSN, CAN-FD, Octal/Quad SPI, Crypto, PUF
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5
Image Subsystem
5.2
LCD Controller (LCDC)
5.2.6
Functional Description
5.2.6.5
RGB Frame Buffer Memory Bitmap
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
4
System Controller
5
Image Subsystem
5.1
Overview
5.2
LCD Controller (LCDC)
5.2.1
Description
5.2.2
Embedded Characteristics
5.2.3
Block Diagram
5.2.4
I/O Lines Description
5.2.5
Product Dependencies
5.2.6
Functional Description
5.2.6.1
Timing Engine Configuration
5.2.6.2
Interrupt Software Operations
5.2.6.3
DMA Software Operations
5.2.6.4
Layer Software Configuration
5.2.6.5
RGB Frame Buffer Memory Bitmap
5.2.6.5.1
1 bpp Through Color Look-up Table
5.2.6.5.2
2 bpp Through Color Look-up Table
5.2.6.5.3
4 bpp Through Color Look-up Table
5.2.6.5.4
8 bpp Through Color Look-up Table
5.2.6.5.5
12 bpp Memory Mapping, RGB 4:4:4
5.2.6.5.6
16 bpp Memory Mapping with Alpha Channel, ARGB 4:4:4:4
5.2.6.5.7
16 bpp Memory Mapping with Alpha Channel, RGBA 4:4:4:4
5.2.6.5.8
16 bpp Memory Mapping with Alpha Channel, RGB 5:6:5
5.2.6.5.9
16 bpp Memory Mapping with Transparency Bit, ARGB 1:5:5:5
5.2.6.5.10
18 bpp Unpacked Memory Mapping, RGB 6:6:6
5.2.6.5.11
18 bpp Packed Memory Mapping, RGB 6:6:6
5.2.6.5.12
19 bpp Unpacked Memory Mapping with Transparency Bit, ARGB 1:6:6:6
5.2.6.5.13
19 bpp Packed Memory Mapping with Transparency Bit, ARGB 1:6:6:6
5.2.6.5.14
24 bpp Unpacked Memory Mapping, RGB 8:8:8
5.2.6.5.15
24 bpp Packed Memory Mapping, RGB 8:8:8
5.2.6.5.16
25 bpp Memory Mapping with Transparency Bit, ARGB 1:8:8:8
5.2.6.5.17
32 bpp Memory Mapping, ARGB 8:8:8:8
5.2.6.5.18
32 bpp Memory Mapping, RGBA 8:8:8:8
5.2.6.6
YCbCr Frame Buffer Memory Mapping
5.2.6.7
Contrast Brightness, Hue, and Saturation
5.2.6.8
Chroma Upsampling Unit
5.2.6.9
Striding
5.2.6.10
Gamma Correction
5.2.6.11
Interlaced Frame Content
5.2.6.12
Color Space Conversion Unit
5.2.6.13
Unified Scaling Engine
5.2.6.14
Color Combine Unit
5.2.6.15
LCDC PWM Controller
5.2.6.16
Register Write Protection
5.2.6.17
LCD Overall Performance
5.2.6.18
Input FIFO
5.2.6.19
Output FIFO
5.2.6.20
Output Timing Generation
5.2.6.21
Output Format
5.2.7
Register Summary
5.3
Low Voltage Differential Signaling Controller (LVDSC)
5.4
2D Graphics Engine (GFX2D)
5.5
Display Serial Interface (DSI)
5.6
Camera Serial Interface (CSI)
5.7
CSI-2 Demultiplexer Controller (CSI2DC)
5.8
Image Sensor Controller (ISC)
6
Audio Subsystem
7
Security and Cryptography Subsystem
8
Connectivity Subsystem
9
USB Subsystem
10
Electrical and Mechanical Characteristics
11
Revision History
Microchip Information
5.2.6.5 RGB Frame Buffer Memory Bitmap
