5.2.7 Register Summary


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00	LCDC_LCDCFG0	31:24
		23:16	CLKDIV[7:0]
		15:8
		7:0					CLKPWMSEL		CLKBYP	CLKPOL
0x04	LCDC_LCDCFG1	31:24							VSPW[9:8]
		23:16	VSPW[7:0]
		15:8							HSPW[9:8]
		7:0	HSPW[7:0]
0x08	LCDC_LCDCFG2	31:24							VBPW[9:8]
		23:16	VBPW[7:0]
		15:8							VFPW[9:8]
		7:0	VFPW[7:0]
0x0C	LCDC_LCDCFG3	31:24							HBPW[9:8]
		23:16	HBPW[7:0]
		15:8							HFPW[9:8]
		7:0	HFPW[7:0]
0x10	LCDC_LCDCFG4	31:24						RPF[10:8]
		23:16	RPF[7:0]
		15:8						PPL[10:8]
		7:0	PPL[7:0]
0x14	LCDC_LCDCFG5	31:24
		23:16	GUARDTIME[7:0]
		15:8			VSPHO	VSPSU	DPI	MODE[2:0]
		7:0	DISPDLY	DITHER		DISPPOL	VSPDLYE	VSPDLYS	VSPOL	HSPOL
0x18	LCDC_LCDCFG6	31:24
		23:16
		15:8	PWMCVAL[7:0]
		7:0				PWMPOL	PWMPS[3:0]
0x1C	LCDC_LCDCFG7	31:24
		23:16
		15:8						ROW[10:8]
		7:0	ROW[7:0]
0x20	LCDC_LCDEN	31:24
		23:16
		15:8
		7:0		CMEN	SDEN		PWMEN	DISPEN	SYNCEN	CLKEN
0x24	LCDC_LCDDIS	31:24
		23:16
		15:8					PWMRST	DISPRST	SYNCRST	CLKRST
		7:0		CMDIS	SDDIS		PWMDIS	DISPDIS	SYNCDIS	CLKDIS
0x28	LCDC_LCDSR	31:24
		23:16
		15:8
		7:0		CMSTS	SDSTS	SIPSTS	PWMSTS	DISPSTS	LCDSTS	CLKSTS
0x2C	LCDC_LCDIER	31:24	WPIE
		23:16
		15:8					HEOIE	OVR2IE	OVR1IE	BASEIE
		7:0				FIFOERRIE	ROWIE	DISPIE	DISIE	SOFIE
0x30	LCDC_LCDIDR	31:24	WPID
		23:16
		15:8					HEOID	OVR2ID	OVR1ID	BASEID
		7:0				FIFOERRID	ROWID	DISPID	DISID	SOFID
0x34	LCDC_LCDIMR	31:24	WPIM
		23:16
		15:8					HEOIM	OVR2IM	OVR1IM	BASEIM
		7:0				FIFOERRIM	ROWIM	DISPIM	DISIM	SOFIM
0x38	LCDC_LCDISR	31:24	WP
		23:16
		15:8					HEO	OVR2	OVR1	BASE
		7:0				FIFOERR	ROW	DISP	DIS	SOF
0x3C	LCDC_ATTRE	31:24
		23:16
		15:8					HEOCL	OVR2CL	OVR1CL	BASECL
		7:0					HEO	OVR2	OVR1	BASE
0x40	LCDC_ATTRS	31:24	SIP
		23:16
		15:8					HEOCL	OVR2CL	OVR1CL	BASECL
		7:0					HEO	OVR2	OVR1	BASE
0x44 ... 0x5F	Reserved
0x60	LCDC_BASEIER	31:24
		23:16
		15:8
		7:0						OVF	ERROR	END
0x64	LCDC_BASEIDR	31:24
		23:16
		15:8
		7:0						OVF	ERROR	END
0x68	LCDC_BASEIMR	31:24
		23:16
		15:8
		7:0						OVF	ERROR	END
0x6C	LCDC_BASEISR	31:24
		23:16
		15:8
		7:0						OVF	ERROR	END
0x70	LCDC_BASEEN	31:24
		23:16
		15:8
		7:0								ENABLE
0x74	LCDC_BASECLA	31:24	CLA[29:22]
		23:16	CLA[21:14]
		15:8	CLA[13:6]
		7:0	CLA[5:0]
0x78	LCDC_BASEFBA	31:24	FBA[29:22]
		23:16	FBA[21:14]
		15:8	FBA[13:6]
		7:0	FBA[5:0]
0x7C	LCDC_BASECFG0	31:24
		23:16
		15:8
		7:0		BLEN[2:0]
0x80	LCDC_BASECFG1	31:24
		23:16
		15:8							CLUTMODE[1:0]
		7:0	RGBMODE[3:0]					GAM		CLUTEN
0x84	LCDC_BASECFG2	31:24	XSTRIDE[31:24]
		23:16	XSTRIDE[23:16]
		15:8	XSTRIDE[15:8]
		7:0	XSTRIDE[7:0]
0x88	LCDC_BASECFG3	31:24
		23:16	RDEF[7:0]
		15:8	GDEF[7:0]
		7:0	BDEF[7:0]
0x8C	LCDC_BASECFG4	31:24
		23:16
		15:8
		7:0				DISCEN			REP	DMA
0x90	LCDC_BASECFG5	31:24						DISCYPOS[10:8]
		23:16	DISCYPOS[7:0]
		15:8						DISCXPOS[10:8]
		7:0	DISCXPOS[7:0]
0x94	LCDC_BASECFG6	31:24						DISCYSIZE[10:8]
		23:16	DISCYSIZE[7:0]
		15:8						DISCXSIZE[10:8]
		7:0	DISCXSIZE[7:0]
0x98 ... 0xE3	Reserved
0xE4	LCDC_WPMR	31:24	WPKEY[7:0]
		23:16
		15:8		HEWPCRE	HEWPITE	HEWPCFGE	O2WPCRE	O2WPITE	O2WPCFGE	O1WPCRE
		7:0	O1WPITE	O1WPCFGE	BWPCRE	BWPITE	BWPCFGE	WPCRE	WPITE	WPCFGE
0xE8	LCDC_WPSR	31:24
		23:16	WPVSRC[15:8]
		15:8	WPVSRC[7:0]
		7:0						SEQE	CGD	WPVS
0xEC ... 0x015F	Reserved
0x0160	LCDC_OVR1IER	31:24
		23:16
		15:8
		7:0						OVF	ERROR	END
0x0164	LCDC_OVR1IDR	31:24
		23:16
		15:8
		7:0						OVF	ERROR	END
0x0168	LCDC_OVR1IMR	31:24
		23:16
		15:8
		7:0						OVF	ERROR	END
0x016C	LCDC_OVR1ISR	31:24
		23:16
		15:8
		7:0						OVF	ERROR	END
0x0170	LCDC_OVR1EN	31:24
		23:16
		15:8
		7:0								ENABLE
0x0174	LCDC_OVR1CLA	31:24	CLA[29:22]
		23:16	CLA[21:14]
		15:8	CLA[13:6]
		7:0	CLA[5:0]
0x0178	LCDC_OVR1FBA	31:24	FBA[31:24]
		23:16	FBA[23:16]
		15:8	FBA[15:8]
		7:0	FBA[7:0]
0x017C	LCDC_OVR1CFG0	31:24
		23:16
		15:8
		7:0		BLEN[2:0]
0x0180	LCDC_OVR1CFG1	31:24
		23:16
		15:8							CLUTMODE[1:0]
		7:0	RGBMODE[3:0]					GAM		CLUTEN
0x0184	LCDC_OVR1CFG2	31:24						YPOS[10:8]
		23:16	YPOS[7:0]
		15:8						XPOS[10:8]
		7:0	XPOS[7:0]
0x0188	LCDC_OVR1CFG3	31:24						YSIZE[10:8]
		23:16	YSIZE[7:0]
		15:8						XSIZE[10:8]
		7:0	XSIZE[7:0]
0x018C	LCDC_OVR1CFG4	31:24	XSTRIDE[31:24]
		23:16	XSTRIDE[23:16]
		15:8	XSTRIDE[15:8]
		7:0	XSTRIDE[7:0]
0x0190	LCDC_OVR1CFG5	31:24	PSTRIDE[31:24]
		23:16	PSTRIDE[23:16]
		15:8	PSTRIDE[15:8]
		7:0	PSTRIDE[7:0]
0x0194	LCDC_OVR1CFG6	31:24	ADEF[7:0]
		23:16	RDEF[7:0]
		15:8	GDEF[7:0]
		7:0	BDEF[7:0]
0x0198	LCDC_OVR1CFG7	31:24
		23:16	RKEY[7:0]
		15:8	GKEY[7:0]
		7:0	BKEY[7:0]
0x019C	LCDC_OVR1CFG8	31:24
		23:16	RMASK[7:0]
		15:8	GMASK[7:0]
		7:0	BMASK[7:0]
0x01A0	LCDC_OVR1CFG9	31:24	A1[7:0]
		23:16	A0[7:0]
		15:8	DFACTA[1:0]		DFACTC[2:0]			SFACTA[1:0]		SFACTC[2]
		7:0	SFACTC[1:0]				DSTKEY	CRKEY	REP	DMA
0x01A4 ... 0x025F	Reserved
0x0260	LCDC_OVR2IER	31:24
		23:16
		15:8
		7:0						OVF	ERROR	END
0x0264	LCDC_OVR2IDR	31:24
		23:16
		15:8
		7:0						OVF	ERROR	END
0x0268	LCDC_OVR2IMR	31:24
		23:16
		15:8
		7:0						OVF	ERROR	END
0x026C	LCDC_OVR2ISR	31:24
		23:16
		15:8
		7:0						OVF	ERROR	END
0x0270	LCDC_OVR2EN	31:24
		23:16
		15:8
		7:0								ENABLE
0x0274	LCDC_OVR2CLA	31:24	CLA[29:22]
		23:16	CLA[21:14]
		15:8	CLA[13:6]
		7:0	CLA[5:0]
0x0278	LCDC_OVR2FBA	31:24	FBA[31:24]
		23:16	FBA[23:16]
		15:8	FBA[15:8]
		7:0	FBA[7:0]
0x027C	LCDC_OVR2CFG0	31:24
		23:16
		15:8
		7:0		BLEN[2:0]
0x0280	LCDC_OVR2CFG1	31:24
		23:16
		15:8							CLUTMODE[1:0]
		7:0	RGBMODE[3:0]					GAM		CLUTEN
0x0284	LCDC_OVR2CFG2	31:24						YPOS[10:8]
		23:16	YPOS[7:0]
		15:8						XPOS[10:8]
		7:0	XPOS[7:0]
0x0288	LCDC_OVR2CFG3	31:24						YSIZE[10:8]
		23:16	YSIZE[7:0]
		15:8						XSIZE[10:8]
		7:0	XSIZE[7:0]
0x028C	LCDC_OVR2CFG4	31:24	XSTRIDE[31:24]
		23:16	XSTRIDE[23:16]
		15:8	XSTRIDE[15:8]
		7:0	XSTRIDE[7:0]
0x0290	LCDC_OVR2CFG5	31:24	PSTRIDE[31:24]
		23:16	PSTRIDE[23:16]
		15:8	PSTRIDE[15:8]
		7:0	PSTRIDE[7:0]
0x0294	LCDC_OVR2CFG6	31:24	ADEF[7:0]
		23:16	RDEF[7:0]
		15:8	GDEF[7:0]
		7:0	BDEF[7:0]
0x0298	LCDC_OVR2CFG7	31:24
		23:16	RKEY[7:0]
		15:8	GKEY[7:0]
		7:0	BKEY[7:0]
0x029C	LCDC_OVR2CFG8	31:24
		23:16	RMASK[7:0]
		15:8	GMASK[7:0]
		7:0	BMASK[7:0]
0x02A0	LCDC_OVR2CFG9	31:24	A1[7:0]
		23:16	A0[7:0]
		15:8	DFACTA[1:0]		DFACTC[2:0]			SFACTA[1:0]		SFACTC[2]
		7:0	SFACTC[1:0]				DSTKEY	CRKEY	REP	DMA
0x02A4 ... 0x035F	Reserved
0x0360	LCDC_HEOIER	31:24
		23:16						CROVF	CRERROR	CREND
		15:8						CBOVF	CBERROR	CBEND
		7:0						OVF	ERROR	END
0x0364	LCDC_HEOIDR	31:24
		23:16						CROVF	CRERROR	CREND
		15:8						CBOVF	CBERROR	CBEND
		7:0						OVF	ERROR	END
0x0368	LCDC_HEOIMR	31:24
		23:16						CROVF	CRERROR	CREND
		15:8						CBOVF	CBERROR	CBEND
		7:0						OVF	ERROR	END
0x036C	LCDC_HEOISR	31:24
		23:16						CROVF	CRERROR	CREND
		15:8						CBOVF	CBERROR	CBEND
		7:0						OVF	ERROR	END
0x0370	LCDC_HEOEN	31:24
		23:16
		15:8
		7:0								ENABLE
0x0374	LCDC_HEOCLA	31:24	CLA[29:22]
		23:16	CLA[21:14]
		15:8	CLA[13:6]
		7:0	CLA[5:0]
0x0378	LCDC_HEOYFBA0	31:24	FBA[31:24]
		23:16	FBA[23:16]
		15:8	FBA[15:8]
		7:0	FBA[7:0]
0x037C	LCDC_HEOCBFBA0	31:24	CBFBA[31:24]
		23:16	CBFBA[23:16]
		15:8	CBFBA[15:8]
		7:0	CBFBA[7:0]
0x0380	LCDC_HEOCRFBA0	31:24	CRFBA[31:24]
		23:16	CRFBA[23:16]
		15:8	CRFBA[15:8]
		7:0	CRFBA[7:0]
0x0384	LCDC_HEOYFBA1	31:24	FBA[31:24]
		23:16	FBA[23:16]
		15:8	FBA[15:8]
		7:0	FBA[7:0]
0x0388	LCDC_HEOCBFBA1	31:24	CBFBA[31:24]
		23:16	CBFBA[23:16]
		15:8	CBFBA[15:8]
		7:0	CBFBA[7:0]
0x038C	LCDC_HEOCRFBA1	31:24	CRFBA[31:24]
		23:16	CRFBA[23:16]
		15:8	CRFBA[15:8]
		7:0	CRFBA[7:0]
0x0390	LCDC_HEOCFG0	31:24
		23:16
		15:8						BLENCC[2:0]
		7:0		BLEN[2:0]
0x0394	LCDC_HEOCFG1	31:24								ILD
		23:16								YCC422ROT
		15:8	YCCMODE[3:0]						CLUTMODE[1:0]
		7:0	RGBMODE[3:0]					GAM	YCCEN	CLUTEN
0x0398	LCDC_HEOCFG2	31:24						YPOS[10:8]
		23:16	YPOS[7:0]
		15:8						XPOS[10:8]
		7:0	XPOS[7:0]
0x039C	LCDC_HEOCFG3	31:24						YSIZE[10:8]
		23:16	YSIZE[7:0]
		15:8						XSIZE[10:8]
		7:0	XSIZE[7:0]
0x03A0	LCDC_HEOCFG4	31:24						YMEMSIZE[10:8]
		23:16	YMEMSIZE[7:0]
		15:8						XMEMSIZE[10:8]
		7:0	XMEMSIZE[7:0]
0x03A4	LCDC_HEOCFG5	31:24	XSTRIDE[31:24]
		23:16	XSTRIDE[23:16]
		15:8	XSTRIDE[15:8]
		7:0	XSTRIDE[7:0]
0x03A8	LCDC_HEOCFG6	31:24	PSTRIDE[31:24]
		23:16	PSTRIDE[23:16]
		15:8	PSTRIDE[15:8]
		7:0	PSTRIDE[7:0]
0x03AC	LCDC_HEOCFG7	31:24	CCXSTRIDE[31:24]
		23:16	CCXSTRIDE[23:16]
		15:8	CCXSTRIDE[15:8]
		7:0	CCXSTRIDE[7:0]
0x03B0	LCDC_HEOCFG8	31:24	CCPSTRIDE[31:24]
		23:16	CCPSTRIDE[23:16]
		15:8	CCPSTRIDE[15:8]
		7:0	CCPSTRIDE[7:0]
0x03B4	LCDC_HEOCFG9	31:24	ADEF[7:0]
		23:16	RDEF[7:0]
		15:8	GDEF[7:0]
		7:0	BDEF[7:0]
0x03B8	LCDC_HEOCFG10	31:24
		23:16	RKEY[7:0]
		15:8	GKEY[7:0]
		7:0	BKEY[7:0]
0x03BC	LCDC_HEOCFG11	31:24
		23:16	RMASK[7:0]
		15:8	GMASK[7:0]
		7:0	BMASK[7:0]
0x03C0	LCDC_HEOCFG12	31:24	A1[7:0]
		23:16	A0[7:0]
		15:8	DFACTA[1:0]		DFACTC[2:0]			SFACTA[1:0]		SFACTC[2]
		7:0	SFACTC[1:0]		VIDPRI		DSTKEY	CRKEY	REP	DMA
0x03C4	LCDC_HEOCFG13	31:24
		23:16
		15:8
		7:0				BL				ENABLE
0x03C8	LCDC_HEOCFG14	31:24					CONT[11:8]
		23:16	CONT[7:0]
		15:8						BRIGHT[10:8]
		7:0	BRIGHT[7:0]
0x03CC	LCDC_HEOCFG15	31:24					SAT[11:8]
		23:16	SAT[7:0]
		15:8								HUE[8]
		7:0	HUE[7:0]
0x03D0	LCDC_HEOCFG16	31:24				RCBGAIN[12:8]
		23:16	RCBGAIN[7:0]
		15:8				RYGAIN[12:8]
		7:0	RYGAIN[7:0]
0x03D4	LCDC_HEOCFG17	31:24
		23:16
		15:8				RCRGAIN[12:8]
		7:0	RCRGAIN[7:0]
0x03D8	LCDC_HEOCFG18	31:24				GCBGAIN[12:8]
		23:16	GCBGAIN[7:0]
		15:8				GYGAIN[12:8]
		7:0	GYGAIN[7:0]
0x03DC	LCDC_HEOCFG19	31:24
		23:16
		15:8				GCRGAIN[12:8]
		7:0	GCRGAIN[7:0]
0x03E0	LCDC_HEOCFG20	31:24				BCBGAIN[12:8]
		23:16	BCBGAIN[7:0]
		15:8				BYGAIN[12:8]
		7:0	BYGAIN[7:0]
0x03E4	LCDC_HEOCFG21	31:24
		23:16
		15:8				BCRGAIN[12:8]
		7:0	BCRGAIN[7:0]
0x03E8	LCDC_HEOCFG22	31:24
		23:16
		15:8
		7:0						CROFF	CBOFF	YOFF
0x03EC	LCDC_HEOCFG23	31:24
		23:16
		15:8
		7:0			HXSCEN	HXSYEN			VXSCEN	VXSYEN
0x03F0	LCDC_HEOCFG24	31:24
		23:16	VXSYFACT[23:16]
		15:8	VXSYFACT[15:8]
		7:0	VXSYFACT[7:0]
0x03F4	LCDC_HEOCFG25	31:24
		23:16	VXSCFACT[23:16]
		15:8	VXSCFACT[15:8]
		7:0	VXSCFACT[7:0]
0x03F8	LCDC_HEOCFG26	31:24
		23:16	HXSYFACT[23:16]
		15:8	HXSYFACT[15:8]
		7:0	HXSYFACT[7:0]
0x03FC	LCDC_HEOCFG27	31:24
		23:16	HXSCFACT[23:16]
		15:8	HXSCFACT[15:8]
		7:0	HXSCFACT[7:0]
0x0400	LCDC_HEOCFG28	31:24					VXSCOFF1[3:0]
		23:16					VXSCOFF[3:0]
		15:8					VXSYOFF1[3:0]
		7:0					VXSYOFF[3:0]
0x0404	LCDC_HEOCFG29	31:24
		23:16					HXSCOFF[3:0]
		15:8
		7:0					HXSYOFF[3:0]
0x0408	LCDC_HEOCFG30	31:24							VXSCCFG1[1:0]
		23:16		VXSCBICU	VXSC1201N	VXSCTAP2			VXSCCFG[1:0]
		15:8							VXSYCFG1[1:0]
		7:0		VXSYBICU	VXSY1201N	VXSYTAP2			VXSYCFG[1:0]
0x040C	LCDC_HEOCFG31	31:24
		23:16			HXSCBICU	HXSCTAP2			HXSCCFG[1:0]
		15:8
		7:0			HXSYBICU	HXSYTAP2			HXSYCFG[1:0]
0x0410	LCDC_HEOVTAP10P0	31:24				TAP1[12:8]
		23:16	TAP1[7:0]
		15:8				TAP0[12:8]
		7:0	TAP0[7:0]
0x0414	LCDC_HEOVTAP32P0	31:24				TAP3[12:8]
		23:16	TAP3[7:0]
		15:8				TAP2[12:8]
		7:0	TAP2[7:0]
0x0418	LCDC_HEOVTAP10P1	31:24				TAP1[12:8]
		23:16	TAP1[7:0]
		15:8				TAP0[12:8]
		7:0	TAP0[7:0]
0x041C	LCDC_HEOVTAP32P1	31:24				TAP3[12:8]
		23:16	TAP3[7:0]
		15:8				TAP2[12:8]
		7:0	TAP2[7:0]
0x0420	LCDC_HEOVTAP10P2	31:24				TAP1[12:8]
		23:16	TAP1[7:0]
		15:8				TAP0[12:8]
		7:0	TAP0[7:0]
0x0424	LCDC_HEOVTAP32P2	31:24				TAP3[12:8]
		23:16	TAP3[7:0]
		15:8				TAP2[12:8]
		7:0	TAP2[7:0]
0x0428	LCDC_HEOVTAP10P3	31:24				TAP1[12:8]
		23:16	TAP1[7:0]
		15:8				TAP0[12:8]
		7:0	TAP0[7:0]
0x042C	LCDC_HEOVTAP32P3	31:24				TAP3[12:8]
		23:16	TAP3[7:0]
		15:8				TAP2[12:8]
		7:0	TAP2[7:0]
0x0430	LCDC_HEOVTAP10P4	31:24				TAP1[12:8]
		23:16	TAP1[7:0]
		15:8				TAP0[12:8]
		7:0	TAP0[7:0]
0x0434	LCDC_HEOVTAP32P4	31:24				TAP3[12:8]
		23:16	TAP3[7:0]
		15:8				TAP2[12:8]
		7:0	TAP2[7:0]
0x0438	LCDC_HEOVTAP10P5	31:24				TAP1[12:8]
		23:16	TAP1[7:0]
		15:8				TAP0[12:8]
		7:0	TAP0[7:0]
0x043C	LCDC_HEOVTAP32P5	31:24				TAP3[12:8]
		23:16	TAP3[7:0]
		15:8				TAP2[12:8]
		7:0	TAP2[7:0]
0x0440	LCDC_HEOVTAP10P6	31:24				TAP1[12:8]
		23:16	TAP1[7:0]
		15:8				TAP0[12:8]
		7:0	TAP0[7:0]
0x0444	LCDC_HEOVTAP32P6	31:24				TAP3[12:8]
		23:16	TAP3[7:0]
		15:8				TAP2[12:8]
		7:0	TAP2[7:0]
0x0448	LCDC_HEOVTAP10P7	31:24				TAP1[12:8]
		23:16	TAP1[7:0]
		15:8				TAP0[12:8]
		7:0	TAP0[7:0]
0x044C	LCDC_HEOVTAP32P7	31:24				TAP3[12:8]
		23:16	TAP3[7:0]
		15:8				TAP2[12:8]
		7:0	TAP2[7:0]
0x0450	LCDC_HEOVTAP10P8	31:24				TAP1[12:8]
		23:16	TAP1[7:0]
		15:8				TAP0[12:8]
		7:0	TAP0[7:0]
0x0454	LCDC_HEOVTAP32P8	31:24				TAP3[12:8]
		23:16	TAP3[7:0]
		15:8				TAP2[12:8]
		7:0	TAP2[7:0]
0x0458	LCDC_HEOVTAP10P9	31:24				TAP1[12:8]
		23:16	TAP1[7:0]
		15:8				TAP0[12:8]
		7:0	TAP0[7:0]
0x045C	LCDC_HEOVTAP32P9	31:24				TAP3[12:8]
		23:16	TAP3[7:0]
		15:8				TAP2[12:8]
		7:0	TAP2[7:0]
0x0460	LCDC_HEOVTAP10P10	31:24				TAP1[12:8]
		23:16	TAP1[7:0]
		15:8				TAP0[12:8]
		7:0	TAP0[7:0]
0x0464	LCDC_HEOVTAP32P10	31:24				TAP3[12:8]
		23:16	TAP3[7:0]
		15:8				TAP2[12:8]
		7:0	TAP2[7:0]
0x0468	LCDC_HEOVTAP10P11	31:24				TAP1[12:8]
		23:16	TAP1[7:0]
		15:8				TAP0[12:8]
		7:0	TAP0[7:0]
0x046C	LCDC_HEOVTAP32P11	31:24				TAP3[12:8]
		23:16	TAP3[7:0]
		15:8				TAP2[12:8]
		7:0	TAP2[7:0]
0x0470	LCDC_HEOVTAP10P12	31:24				TAP1[12:8]
		23:16	TAP1[7:0]
		15:8				TAP0[12:8]
		7:0	TAP0[7:0]
0x0474	LCDC_HEOVTAP32P12	31:24				TAP3[12:8]
		23:16	TAP3[7:0]
		15:8				TAP2[12:8]
		7:0	TAP2[7:0]
0x0478	LCDC_HEOVTAP10P13	31:24				TAP1[12:8]
		23:16	TAP1[7:0]
		15:8				TAP0[12:8]
		7:0	TAP0[7:0]
0x047C	LCDC_HEOVTAP32P13	31:24				TAP3[12:8]
		23:16	TAP3[7:0]
		15:8				TAP2[12:8]
		7:0	TAP2[7:0]
0x0480	LCDC_HEOVTAP10P14	31:24				TAP1[12:8]
		23:16	TAP1[7:0]
		15:8				TAP0[12:8]
		7:0	TAP0[7:0]
0x0484	LCDC_HEOVTAP32P14	31:24				TAP3[12:8]
		23:16	TAP3[7:0]
		15:8				TAP2[12:8]
		7:0	TAP2[7:0]
0x0488	LCDC_HEOVTAP10P15	31:24				TAP1[12:8]
		23:16	TAP1[7:0]
		15:8				TAP0[12:8]
		7:0	TAP0[7:0]
0x048C	LCDC_HEOVTAP32P15	31:24				TAP3[12:8]
		23:16	TAP3[7:0]
		15:8				TAP2[12:8]
		7:0	TAP2[7:0]
0x0490	LCDC_HEOHTAP10P0	31:24				TAP1[12:8]
		23:16	TAP1[7:0]
		15:8				TAP0[12:8]
		7:0	TAP0[7:0]
0x0494	LCDC_HEOHTAP32P0	31:24				TAP3[12:8]
		23:16	TAP3[7:0]
		15:8				TAP2[12:8]
		7:0	TAP2[7:0]
0x0498	LCDC_HEOHTAP10P1	31:24				TAP1[12:8]
		23:16	TAP1[7:0]
		15:8				TAP0[12:8]
		7:0	TAP0[7:0]
0x049C	LCDC_HEOHTAP32P1	31:24				TAP3[12:8]
		23:16	TAP3[7:0]
		15:8				TAP2[12:8]
		7:0	TAP2[7:0]
0x04A0	LCDC_HEOHTAP10P2	31:24				TAP1[12:8]
		23:16	TAP1[7:0]
		15:8				TAP0[12:8]
		7:0	TAP0[7:0]
0x04A4	LCDC_HEOHTAP32P2	31:24				TAP3[12:8]
		23:16	TAP3[7:0]
		15:8				TAP2[12:8]
		7:0	TAP2[7:0]
0x04A8	LCDC_HEOHTAP10P3	31:24				TAP1[12:8]
		23:16	TAP1[7:0]
		15:8				TAP0[12:8]
		7:0	TAP0[7:0]
0x04AC	LCDC_HEOHTAP32P3	31:24				TAP3[12:8]
		23:16	TAP3[7:0]
		15:8				TAP2[12:8]
		7:0	TAP2[7:0]
0x04B0	LCDC_HEOHTAP10P4	31:24				TAP1[12:8]
		23:16	TAP1[7:0]
		15:8				TAP0[12:8]
		7:0	TAP0[7:0]
0x04B4	LCDC_HEOHTAP32P4	31:24				TAP3[12:8]
		23:16	TAP3[7:0]
		15:8				TAP2[12:8]
		7:0	TAP2[7:0]
0x04B8	LCDC_HEOHTAP10P5	31:24				TAP1[12:8]
		23:16	TAP1[7:0]
		15:8				TAP0[12:8]
		7:0	TAP0[7:0]
0x04BC	LCDC_HEOHTAP32P5	31:24				TAP3[12:8]
		23:16	TAP3[7:0]
		15:8				TAP2[12:8]
		7:0	TAP2[7:0]
0x04C0	LCDC_HEOHTAP10P6	31:24				TAP1[12:8]
		23:16	TAP1[7:0]
		15:8				TAP0[12:8]
		7:0	TAP0[7:0]
0x04C4	LCDC_HEOHTAP32P6	31:24				TAP3[12:8]
		23:16	TAP3[7:0]
		15:8				TAP2[12:8]
		7:0	TAP2[7:0]
0x04C8	LCDC_HEOHTAP10P7	31:24				TAP1[12:8]
		23:16	TAP1[7:0]
		15:8				TAP0[12:8]
		7:0	TAP0[7:0]
0x04CC	LCDC_HEOHTAP32P7	31:24				TAP3[12:8]
		23:16	TAP3[7:0]
		15:8				TAP2[12:8]
		7:0	TAP2[7:0]
0x04D0	LCDC_HEOHTAP10P8	31:24				TAP1[12:8]
		23:16	TAP1[7:0]
		15:8				TAP0[12:8]
		7:0	TAP0[7:0]
0x04D4	LCDC_HEOHTAP32P8	31:24				TAP3[12:8]
		23:16	TAP3[7:0]
		15:8				TAP2[12:8]
		7:0	TAP2[7:0]
0x04D8	LCDC_HEOHTAP10P9	31:24				TAP1[12:8]
		23:16	TAP1[7:0]
		15:8				TAP0[12:8]
		7:0	TAP0[7:0]
0x04DC	LCDC_HEOHTAP32P9	31:24				TAP3[12:8]
		23:16	TAP3[7:0]
		15:8				TAP2[12:8]
		7:0	TAP2[7:0]
0x04E0	LCDC_HEOHTAP10P10	31:24				TAP1[12:8]
		23:16	TAP1[7:0]
		15:8				TAP0[12:8]
		7:0	TAP0[7:0]
0x04E4	LCDC_HEOHTAP32P10	31:24				TAP3[12:8]
		23:16	TAP3[7:0]
		15:8				TAP2[12:8]
		7:0	TAP2[7:0]
0x04E8	LCDC_HEOHTAP10P11	31:24				TAP1[12:8]
		23:16	TAP1[7:0]
		15:8				TAP0[12:8]
		7:0	TAP0[7:0]
0x04EC	LCDC_HEOHTAP32P11	31:24				TAP3[12:8]
		23:16	TAP3[7:0]
		15:8				TAP2[12:8]
		7:0	TAP2[7:0]
0x04F0	LCDC_HEOHTAP10P12	31:24				TAP1[12:8]
		23:16	TAP1[7:0]
		15:8				TAP0[12:8]
		7:0	TAP0[7:0]
0x04F4	LCDC_HEOHTAP32P12	31:24				TAP3[12:8]
		23:16	TAP3[7:0]
		15:8				TAP2[12:8]
		7:0	TAP2[7:0]
0x04F8	LCDC_HEOHTAP10P13	31:24				TAP1[12:8]
		23:16	TAP1[7:0]
		15:8				TAP0[12:8]
		7:0	TAP0[7:0]
0x04FC	LCDC_HEOHTAP32P13	31:24				TAP3[12:8]
		23:16	TAP3[7:0]
		15:8				TAP2[12:8]
		7:0	TAP2[7:0]
0x0500	LCDC_HEOHTAP10P14	31:24				TAP1[12:8]
		23:16	TAP1[7:0]
		15:8				TAP0[12:8]
		7:0	TAP0[7:0]
0x0504	LCDC_HEOHTAP32P14	31:24				TAP3[12:8]
		23:16	TAP3[7:0]
		15:8				TAP2[12:8]
		7:0	TAP2[7:0]
0x0508	LCDC_HEOHTAP10P15	31:24				TAP1[12:8]
		23:16	TAP1[7:0]
		15:8				TAP0[12:8]
		7:0	TAP0[7:0]
0x050C	LCDC_HEOHTAP32P15	31:24				TAP3[12:8]
		23:16	TAP3[7:0]
		15:8				TAP2[12:8]
		7:0	TAP2[7:0]
0x0510 ... 0x06FF	Reserved
0x0700	LCDC_BASECLUT0	31:24	ACLUT[7:0]
		23:16	RCLUT[7:0]
		15:8	GCLUT[7:0]
		7:0	BCLUT[7:0]
...
0x0AFC	LCDC_BASECLUT255	31:24	ACLUT[7:0]
		23:16	RCLUT[7:0]
		15:8	GCLUT[7:0]
		7:0	BCLUT[7:0]
0x0B00	LCDC_OVR1CLUT0	31:24	ACLUT[7:0]
		23:16	RCLUT[7:0]
		15:8	GCLUT[7:0]
		7:0	BCLUT[7:0]
...
0x0EFC	LCDC_OVR1CLUT255	31:24	ACLUT[7:0]
		23:16	RCLUT[7:0]
		15:8	GCLUT[7:0]
		7:0	BCLUT[7:0]
0x0F00	LCDC_OVR2CLUT0	31:24	ACLUT[7:0]
		23:16	RCLUT[7:0]
		15:8	GCLUT[7:0]
		7:0	BCLUT[7:0]
...
0x12FC	LCDC_OVR2CLUT255	31:24	ACLUT[7:0]
		23:16	RCLUT[7:0]
		15:8	GCLUT[7:0]
		7:0	BCLUT[7:0]
0x1300	LCDC_HEOCLUT0	31:24	ACLUT[7:0]
		23:16	RCLUT[7:0]
		15:8	GCLUT[7:0]
		7:0	BCLUT[7:0]
...
0x16FC	LCDC_HEOCLUT255	31:24	ACLUT[7:0]
		23:16	RCLUT[7:0]
		15:8	GCLUT[7:0]
		7:0	BCLUT[7:0]