45.7.20 TWIHS FIFO Mode Register

This registers reads “0” if the FIFO is disabled (see TWI_CR to enable/disable the internal FIFO).

Name: TWIHS_FMR
Offset: 0x50
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
   RXFTHRES[5:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 2322212019181716 
   TXFTHRES[5:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
   RXRDYM[1:0]  TXRDYM[1:0] 
Access R/WR/WR/WR/W 
Reset 0000 

Bits 29:24 – RXFTHRES[5:0] Receive FIFO Threshold

ValueDescription
0–16

Defines the Receive FIFO threshold value (number of data). RXFTH flag in TWIHS_FSR will be set when Receive FIFO goes from “below” threshold state to “equal or above” threshold state.

Bits 21:16 – TXFTHRES[5:0] Transmit FIFO Threshold

ValueDescription
0–16

Defines the Transmit FIFO threshold value (number of data). TXFTH flag in TWIHS_FSR will be set when Transmit FIFO goes from “above” threshold state to “equal or below” threshold state.

Bits 5:4 – RXRDYM[1:0] Receiver Ready Mode

If FIFOs are enabled, the RXRDY flag (in TWIHS_SR) behaves as follows.

ValueNameDescription
0 ONE_DATA

RXRDY will be at level ‘1’ when at least one unread data is in the Receive FIFO

1 TWO_DATA

RXRDY will be at level ‘1’ when at least two unread data are in the Receive FIFO

2 FOUR_DATA

RXRDY will be at level ‘1’ when at least four unread data are in the Receive FIFO

Bits 1:0 – TXRDYM[1:0] Transmitter Ready Mode

If FIFOs are enabled, the TXRDY flag (in TWIHS_SR) behaves as follows.

ValueNameDescription
0 ONE_DATA

TXRDY will be at level ‘1’ when at least one data can be written in the Transmit FIFO

1 TWO_DATA

TXRDY will be at level ‘1’ when at least two data can be written in the Transmit FIFO

2 FOUR_DATA

TXRDY will be at level ‘1’ when at least four data can be written in the Transmit FIFO