60.5.9 SHA Input Data Register x

Name: SHA_IDATARx
Offset: 0x40 + x*0x04 [x=0..15]
Reset: 
Property: Write-only

Bit 3130292827262524 
 IDATA[31:24] 
Access WWWWWWWW 
Reset  
Bit 2322212019181716 
 IDATA[23:16] 
Access WWWWWWWW 
Reset  
Bit 15141312111098 
 IDATA[15:8] 
Access WWWWWWWW 
Reset  
Bit 76543210 
 IDATA[7:0] 
Access WWWWWWWW 
Reset  

Bits 31:0 – IDATA[31:0] Input Data

32-bit Input Data registers load the data block used for hash processing.

These registers are write-only to prevent reading of input data by another application.

SHA_IDATAR0 corresponds to the first word of the block, SHA_IDATAR15 to the last word of the last block in case SHA algorithm is set to SHA1, SHA224, SHA256, or SHA_IODATAR15 to the last word of the block if SHA algorithm is SHA384 or SHA512 (see SHA Input/Output Data Register x).

SHA_IDATARx can be also written to configure the hash result of the previous fragment of a message when starting the processing of the next fragment when the SHA has processed another message in between fragments.