37.2.4.2 I3C Address Header

The I3C Address Header follows either a Start or a Restart condition and follows the same format as an I2C Address Header – 7 Address bits, one R/W bit, and one ACK/NACK bit.

The Address Header following a Start Condition (but not a Restart condition) is subject to arbitration. This means that multiple devices may be attempting to drive an address on the bus using the SDA lines and is, therefore, transmitted in Open-Drain mode. Refer to I3C Address Arbitration for more information.

Figure 37-9. Open-Drain Generic Address Header Timing Diagram

The Address Header following a Restart condition is not subject to any arbitration, meaning only the Controller drives an address on the bus and is, therefore, always transmitted in Push-Pull mode with the exception of ACK/NACK bit. Figure 37-10 shows a non-arbitrable Address Header in Push-Pull mode.

Figure 37-10. Non-Arbitrable Address Header in Push-Pull Mode
The device (Controller or Target) transmitting the 7-bit address in the address header also transmits the R/W bit in the address header. The device transmits a low signal on SDA line (R/W bit = 0) to represent Write mode (the Controller writing to the Target). The device transmits a high signal on SDA line (R/W bit = 1) to represent Read mode (the Controller reading from the Target). The R/W bit follows the same signaling (Open-Drain or Push-Pull) as that of the 7 Address bits preceding it. In a Private I3C/I2C Transaction, the status of the R/W bit is captured in the RNW bits.

Once the device transmits the first eight bits of the address header on the bus, it waits for the other device (the Controller waits for the Target, the Target waits for the Controller) to acknowledge (or not acknowledge) the request. This is done through the ninth ACK/NACK bit in the address header. The ACK/NACK bit is always transmitted in Open-Drain regardless of the signaling used to transmit the first eight bits. The responding device pulls the SDA line low (ACK/NACK bit = 0) to respond with an acknowledge (ACK), whereas the responding device releases the SDA line high (ACK/NACK bit = 1) to respond with a non-acknowledge (NACK). Table 37-6 shows the different conditions when this Target module ACKs and NACKs an address on the bus.

Table 37-6. Address ACK/NACK by Target
Transaction ACK Condition NACK Condition
Broadcast Address Always Never
Private/I2C Read Transaction(1)
Always when ACKP = 0 and data are ready to be transmitted from the TX FIFO (TXFNE = 1)
Or, once when ACKP = 1 and ACKPOS = 1 in addition to data being ready to be transmitted from the TX FIFO (TXFNE = 1)

Always when TX FIFO is empty (TXFNE = 0)

Or, always when ACKP = 1 and ACKPOS = 0
Private/I2C Write Transaction(1,2)

Always when ACKP = 0

Or, once when ACKP = 1 and ACKPOS = 1

Always when ACKP = 1 and ACKPOS = 0
ENTDAA Dynamic Address Assignment
Always when HJCAP = 0 and Target does not have a Dynamic Address assigned

Or, only after Hot-Join has been requested when HJCAP = 1 and Target does not have a Dynamic Address assigned

Before Hot-Join has been requested when HJCAP = 1

Or, any time the Target already has an assigned Dynamic Address
Note:
  1. The Target responds to static address when operating in I2C mode, dynamic address when operating in I3C SDR mode, and both static and dynamic addresses when operating in Static Address SDR mode.
  2. The status of the receive buffer and FIFO (RXBF bit) has no effect on ACK/NACK during Private/I2C Write Transaction.

The following address types can be transmitted on the I3C bus:

  • I2C Static Address
  • I3C Dynamic Address
  • I3C Broadcast Address
  • I3C Hot-Join Address