37.2.12.2.1 Software Force HDR Exit

The module can also be forced out of HDR mode by setting the FHDRE bit. This operation resets the internal state machine to the idle state and OPMD bits are changed back to the appropriate SDR mode. The FDHRE bit is synchronized and takes effect after two rising SCL clock edges. The bit self-clears after the module returns to operating in the SDR mode.

This feature can be useful in auto-recovery from TE0 and TE1 error states without depending on the Controller device to send an HDR Exit Pattern for error recovery. To properly force the module out of HDR mode, the MIPI I3C Specification suggests monitoring the SDA and SCL lines. If both the SDA and SCL lines stay High for at least 60 μs, then the Target accepts that the bus is operating in non-HDR mode, and it is safe to transition back to SDR mode. The 60 μs wait time is derived from the slowest HDR speed. The slowest HDR clock is 10 kHz with a total cycle time of 100 μs. It is assumed that an HDR mode will keep an approximately even duty cycle at slow clock speeds, thus making 60% of the duty cycle (or 60 μs) a safe wait time. The user can use the inbuilt Bus Time-out feature to measure 60 μs and set the FHDRE bit when bus time-out occurs.

Important:
  1. The FHDRE bit can only be set when the module is operating in HDR mode (OPMD = 0b1x), either due to an ENTHDRx CCC or TE0/TE1 error condition.
  2. Setting the FHDRE bit does not prevent the module from detecting an HDR Exit Pattern on the bus. If an HDR Exit Pattern is detected on the bus before two rising SCL edges can occur, the module will still recover safely back to operating in SDR mode.
Warning: The user must use discretion when forcing the module out of HDR mode without identifying a proper HDR Exit Pattern on the bus. Improper usage of the bus may lead to unexpected behavior.