37.4.5 I3CxSTAT0

Note:

Will not self-clear after the event. The user must clear this bit to re-arm.
The bus may be active even when the Target is Idle.
These bits only apply for Private I3C/I²C Transfers. The R/W bit is not captured during non-Private Transactions (like CCC, IBI, or Hot-Join).
These bits are not updated when the device is in sleep. The correct values are loaded at the end of the second instruction cycle after the device wakes up from sleep.
In case of a race condition, user writes always take precedence over hardware events.

Name:	I3CxSTAT0
Address:	0x087, 0x0BA

Status 0


Bit	7	6	5	4	3	2	1	0
	BFREE	OPMD[1:0]		RSTDET	TXBE	RXBF	RNW[1:0]
Access	R/HS/HC	R/HS/HC	R/HS/HC	R/W/HS	R/HS/HC	R/HS/HC	R/C/HS/HC	R/C/HS/HC
Reset	1	0	0	0	1	0	0	0

Bit 7 – BFREE Bus Free Condition Status

Value	Description
1	Bus is idle and there are no transactions happening on the bus
0	Bus is not idle and there is a transaction happening on the bus

Bits 6:5 – OPMD[1:0] Operating Mode Status

Value	Description
11	The Target is operating in I3C mode; The bus is operating in High Data Rate (HDR) mode
10	The Target is operating in Legacy I²C mode; The bus is operating in High Data Rate (HDR) mode
01	The Target is operating in I3C mode; The bus is operating in Single Data Rate (SDR) mode
00	The Target is operating in Legacy I²C mode; The bus is operating in Single Data Rate (SDR) mode

Bit 4 – RSTDET Reset Pattern Detected⁽¹⁾

Value	Description
1	A Target Reset Pattern has been detected on the bus
0	A Target Reset Pattern has not been detected on the bus

Bit 3 – TXBE Transmit Buffer Empty Status

Value	Description
1	I3CxTXB is empty and safe to write
0	I3CxTXB is not empty and must not be written

Bit 2 – RXBF Receive Buffer Full Status

Value	Description
1	Data in I3CxRXB is ready to be read
0	Data in I3CxRXB is not ready to be read

Bits 1:0 – RNW[1:0] Read/nWrite (R/W) Status^{(2, 3, 4)}

Value	Description
11	Reserved
10	The last Private/I²C Transaction that was ACK'd by the Target was a Write operation (Controller writing to Target)
01	The last Private/I²C Transaction that was ACK'd by the Target was a Read operation (Controller reading from Target)
00	The Target is Idle or operating in non-Private/I²C Transaction

Will not self-clear after the event. The user must clear this bit to re-arm. The bus may be active even when the Target is Idle. These bits only apply for Private I3C/I2C Transfers. The R/W bit is not captured during non-Private Transactions (like CCC, IBI, or Hot-Join). These bits are not updated when the device is in sleep. The correct values are loaded at the end of the second instruction cycle after the device wakes up from sleep. In case of a race condition, user writes always take precedence over hardware events.