32.7.17 ADACC

ADC Accumulator Register

See Table 32-4 for more details.

Name:	ADACC
Offset:	0xF70


Bit	15	14	13	12	11	10	9	8
	ADACCH[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	x	x	x	x	x	x	x	x


Bit	7	6	5	4	3	2	1	0
	ADACCL[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	x	x	x	x	x	x	x	x

Bits 15:8 – ADACCH[7:0]

ADC Accumulator Most Significant Byte.

Reset States:

POR/BOR = xxxxxxxx

All Other Resets = uuuuuuuu

Bits 7:0 – ADACCL[7:0]

ADC Accumulator Least Significant Byte.

Reset States:

POR/BOR = xxxxxxxx

All Other Resets = uuuuuuuu

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