3.2.3 Metrology State Flags Register

Name: STATE_FLAG
Property: Read

Bit 3130292827262524 
  SWELL_DET_VCSWELL_DET_VBSWELL_DET_VA SAG_DET_VCSAG_DET_VBSAG_DET_VA 
Access RRRRRR 
Reset 000000 
Bit 2322212019181716 
 CREEP_DET_SPC_OUT_OF_RANGEARCH_DETECT_FAILCREEP_DET_PCREEP_DET_QCREEP_DET_ICCREEP_DET_IBCREEP_DET_IA 
Access RRRRRRRR 
Reset 00000000 
Bit 15141312111098 
 HOST_ID_FAIL        
Access R 
Reset 0 
Bit 76543210 
 ATSENSE_FAIL FREQ_LOCKEDTIMING_Vx[1:0]PH_C_ACTIVEPH_B_ACTIVEPH_A_ACTIVE 
Access RRRRRRR 
Reset 0000000 

Bits 28, 29, 30 – SWELL_DET_Vx Voltage Swell Detected Flag for Channel x

ValueDescription
0 Voltage swell is not detected for the current half line cycle
1 Voltage swell is detected for the current half line cycle

Bits 24, 25, 26 – SAG_DET_Vx Voltage Swell Detected Flag for Channel x

ValueDescription
0 Voltage sag is not detected in the current half line cycle
1 Voltage sag is detected in the current half line cycle

Bit 23 – CREEP_DET_S Total Apparent Power Creep Detected Flag

CREEP_DET_S status flag only updated when enabled (CREEP_S_EN = 1).

ValueDescription
0 Apparent power creep is not detected in the current full line cycle
1 Apparent power creep is detected in the current full line cycle

Bit 22 – PC_OUT_OF_RANGE Phase Corrector Out of Range

Indicates if a set of requested phase correction values are out of range.
ValueDescription
0 Requested phase correction values in range
1 Requested phase correction values out of range

Bit 21 – ARCH_DETECT_FAIL Architecture Detect Failure

Indicates that a proper device architecture was not detected (”SH” or “C”).
ValueDescription
0 A proper device (”SH” or “C”) was detected
1 An improper device (not ”SH” nor “C”) was detected

Bit 20 – CREEP_DET_P Total Active Power Creep Detected Flag

CREEP_DET_P status flag only updated when enabled (CREEP_P_EN = 1).
ValueDescription
0 Active power creep is not detected in the current full line cycle
1 Active power creep is detected in the current full line cycle

Bit 19 – CREEP_DET_Q Total Reactive Power Creep Detected Flag

CREEP_DET_Q status flag only updated when enabled (CREEP_Q_EN = 1).
ValueDescription
0 Reactive power creep is not detected in the current full line cycle
1 Reactive power creep is detected in the current full line cycle

Bits 16, 17, 18 – CREEP_DET_Ix Phase x Current Creep Detected Flag

CREEP_DET_I status flag only updated when enabled (CREEP_I_EN = 1).
ValueDescription
0 Channel x current creep is not detected in the current full line cycle
1 Channel x current creep is detected in the current full line cycle

Bit 15 – HOST_ID_FAIL Host Identification Failure Indication

The detection process determines if the host has an internal ATSense (PIC32CXMTSx) or makes use of an external ATSense (PIC32CXMTC). If a proper ID is not made, this bit is used to show this status.
ValueDescription
0 Proper PIC32CXMTx part successfully identified
1 Failed to identify proper PIC32CXMTx part

Bit 7 – ATSENSE_FAIL ATSENSE State

ValueDescription
0 ATSENSE initialization is successful
1 ATSENSE initialization is failed

Bit 5 – FREQ_LOCKED Frequency Locked Flag

ValueDescription
0 Line frequency is not determined. Using sample count limit for metrology integration period.
1 Line frequency was determined

Bits 4:3 – TIMING_Vx[1:0] Dominant Voltage Channel

Indicates which voltage channel is used for frequency determination and cycle timing. If no voltage phases are active, phase VA is selected by default.
ValueDescription
0 Voltage phase VA is used for timing extraction purposes
1 Voltage phase VB is used for timing extraction purposes
2 Voltage phase VC is used for timing extraction purposes

Bits 0, 1, 2 – PH_x_ACTIVE Phase x is active

ValueDescription
0 Voltage phase x is inactive
1 Voltage phase x is active