2.5.2.2 Hitless Clock Switching: Enable SyncE

The following figure shows the Hitless clock switching for Enable SyncE.

Figure 2-11. Hitless Clock Switching: Enable SyncE

Whenever the ESMC receiver subsystem receives a new QL-value, the selection algorithm compares the incoming QL-value with the already existing local QL-value and makes the appropriate decision.

If the incoming QL-value has higher priority than the existing local QL-value, then the selection algorithm notifies the JAPLL Controller to take necessary action such that the JAPLL locks to the better quality recovered clock and enable the SyncE.

The JAPLL Controller performs the following sequence of steps to enable the SyncE.

  1. ENTER_HOLDOVER:
    • Enable JAPLL hold by setting JA_HOLD to "1" and PRESET_EN to "1" to use the default INT and FRAC preset values.
  2. WAIT_FOR_VALID_LINK:
    • Wait for 200 µs to make sure the JAPLL enters into holdover.
  3. EN_DIS_SYNCE:
    • Switch the FIN of JAPLL to the cdr recovered clock.
    • Now JAPLL starts locking to the recovered clock.
  4. EXIT_HOLDOVER:
    • Set JA_HOLD to "0" and PRESET_EN to "0" to disable JAPLL hold.
  5. Start the averaging algorithm: For more information, see Averaging Algorithm Implementation.