2.5.2.5 Averaging Algorithm Implementation

The following figure shows the sampling algorithm block diagram.

Figure 2-14. Averaging Algorithm

When the start_avg_algo_i signal is asserted, the japll_controller finite state machine executes the averaging algorithm by continuously reading the INT_PD_OUT and FRAC_PD_OUT values of the Phase detector and computes the average values till it reaches the user-specified limit.

The following procedure computes the average value:

  1. Read INT_PD_OUT and FRAC_PD_OUT.
  2. Accumulate the INT_PD_OUT and FRAC_PD_OUT.
  3. Repeat the preceding steps till the count reaches AVG_COUNT specified by the user.
  4. After AVG_COUNT iterations, compute the average value.
  5. Load the JAPLL INT preset using the new computed INT_PRESET.
  6. Extract the INT_PRESET and FRAC_PRESET from the computed average value.

In the event of a clock switching or link loss, JAPLL is programmed to use the computed INT_PRESET and FRAC_PRESET when entering in to hold state using the PRESERT_EN function. During Hold state, the phase detector is shut down, and the outputs of JAPLL are held to their last values.

Averaging algorithm forces the JAPLL outputs to be loaded with the computed INT_PRESET and FRAC_PRESET values in order to make sure the Transmit PLL receives the INT and FRAC values which are closer to the actual and do not exceed the ±7.5 ppm requirement of syncE.

Averaging Algorithm starts when start_avg_algo signal becomes "1" and stops for the following cases:

  • When start_avg_algo signal becomes "0" (occurs during the disable syncE process)
  • When there is a break-link situation