2.5.2.3 Hitless Clock Switching: Disable SyncE

The following figure shows the Hitless clock switching for disable SyncE.

Figure 2-12. Hitless Clock Switching: Disable SyncE

Whenever the ESMC receiver subsystem receives a new QL-value, the selection algorithm compares the incoming QL-value with the already existing local QL-value and makes the appropriate decision.

If the incoming QL-value has a lower priority than the existing local QL-value, then the selection algorithm notifies the JAPLL Controller to take necessary action such that the JAPLL locks to the better-quality local auxiliary clock and disable the SyncE.

The JAPLL Controller performs the following sequence of steps to disable the SyncE:

  • ENTER_HOLDOVER:
    • Enable JAPLL hold by setting JA_HOLD to "1" and PRESET_EN to "1" to use the Averaged INT and FRAC preset values.
  • WAIT_FOR_VALID_LINK:
    • Wait for 200 µs to make sure the JAPLL enters holdover.
  • EN_DIS_SYNCE:
    • Switch the FIN of JAPLL to the local auxiliary clock.
    • Now JAPLL starts locking to the local auxiliary clock.
  • EXIT_HOLDOVER:
    • Set JA_HOLD to "0" and PRESET_EN to "0" to disable JAPLL hold.
  • Stop the averaging algorithm. For more information, see Averaging Algorithm Implementation.