2.5.2.6 Break-link and Make-link Conditions Handling

The following figure shows the break-link and make-link conditions.

Figure 2-15. Break-link and Make-link Conditions

The following are the steps to handle the break-link and make-link condition:

  1. When the frequency monitor logic detects the deviation in the recovered clock frequency, it asserts the link status signal indicating the break-link condition.
  2. ESMC RX SUBSYSTEM generates a no_port_available signal to the JAPLL Controller.
  3. ENTER_HOLDOVER: When no_port_available = 1, Set JA_HOLD to "1" and PRESET_EN to "1" to enable JAPLL hold, to use the previously loaded preset values and proceed to RX_POWERDOWN state.
  4. RX_POWERDOWN: To check the make link condition, FSM periodically checks the cable reinsert sequence by powering up and shutting down the receiver multiple times. Wait for 100 µs in RX_POWERDOWN state and proceed to RX_POWERUP state.
  5. RX_POWERUP: Wait for 4 ms to check the stability of the following signals:
    • rx_ready from transceiver
    • lane_status_lock from transceiver
    • link status from frequency change monitor
    If all the preceding signals are stable at the end of 4 ms time, then FSM proceeds to READ_FLOCK state else return to the RX_POWERDOWN state.
  6. READ_FLOCK: After the make-link condition is successfully verified, the JAPLL FLOCK signal is verified for its stability.
  7. FLOCK_CHECK: Check the FLOCK stability for 200 ms and if the signal is stable, then proceed to EXIT_HOLDOVER state else return to the READ_FLOCK state.
  8. EXIT_HOLDOVER: Set JA_HOLD to "0" and PRESET_EN to "0" to disable the JAPLL hold.

The following table lists the ports and their description.

Table 2-5. Port Description
Port NameDirectionDescription
LANE0_RXD_NINESMC Receiver inverted input
LANE0_RXD_PINESMC Receiver non-inverted input
REF_CLK_PAD_NINInverted reference clock obtained from on-board 156.25 MHz oscillator
REF_CLK_PAD_PINNon-Inverted reference clock obtained from on-board 156.25 MHz oscillator
UART_RX_IF_IINUART receiver interface
reset_iINAsynchronous reset
LANE0_TXD_NOUTESMC Transmitter inverted input
LANE0_TXD_POUTESMC Transmitter non-inverted input
UART_TX_IF_IOUTUART Transmitter interface