30.5.2 Control B

Name: CTRLB
Offset: 0x01
Reset: 0x00
Property: -

Bit 76543210 
     PRESC[3:0] 
Access R/WR/WR/WR/W 
Reset 0000 

Bits 3:0 – PRESC[3:0] Prescaler

This bit field controls the division factor from the peripheral clock (CLK_PER) to the ADC clock (CLK_ADC).
ValueNameDescription
0x0 DIV2 CLK_PER divided by 2
0x1 DIV4 CLK_PER divided by 4
0x2 DIV6 CLK_PER divided by 6
0x3 DIV8 CLK_PER divided by 8
0x4 DIV10 CLK_PER divided by 10
0x5 DIV12 CLK_PER divided by 12
0x6 DIV14 CLK_PER divided by 14
0x7 DIV16 CLK_PER divided by 16
0x8 DIV20 CLK_PER divided by 20
0x9 DIV24 CLK_PER divided by 24
0xA DIV28 CLK_PER divided by 28
0xB DIV32 CLK_PER divided by 32
0xC DIV40 CLK_PER divided by 40
0xD DIV48 CLK_PER divided by 48
0xE DIV56 CLK_PER divided by 56
0xF DIV64 CLK_PER divided by 64