3.6.1.1 Data FIFO Overview

The data FIFO (DFIFO) is a 32-byte deep register bank which stores data with first-in-first-out functionality. The DFIFO has two read and two write interfaces:

  • AVR bus read and write access
  • Direct write access from the RX buffer
  • Direct read access from the TX modulator

The DFIFO additionally implements a configurable fill level status bit with maskable interrupt signaling. Read attempts to an empty DFIFO (underflow) and write attempts a full DFIFO (overflow) are indicated by error flags (DFS.DFUFL and DFS.DFOFL) in the user interface. An error IRQ is triggered if masked in DFI.DFERIM.

A special feature of the DFIFO are the telegram length registers (DFTLH/DFTLL). These registers can be used in DFC.DFDRA = 0 mode to read the number of received bits of the last telegram. This is helpful for unknown telegram lengths, especially if a telegram is not byte-aligned (number of bits is not divisible by 8). The telegram length is written to the registers by the RX buffer once after an EOT is received. The registers are not continuously updated during reception.

The following figure shows a block diagram of the DFIFO.
Figure 3-31. DFIFO Block Diagram

The access mode of the DFIFO is configured by the DFC.DFDRA register bit. If the bit is set to ‘0’, the RX buffer can write to the DFIFO via the direct write interface while the AVR can only read from the DFIFO. This mode must be selected if the ATA8510/15 is receiving data. If the DFC.DFDRA bit is set to ‘1’, the AVR can only write to the DFIFO while the TX modulator is able to read data via the direct read interface. This mode must be selected if the ATA8510/15 is transmitting data.

The DFIFO can trigger an interrupt if a certain fill level is reached. The interrupt can be switched on by setting the data FIFO fill level interrupt mask bit (DFI.DFFLIM) to ‘1’. The required fill level can be configured in the data FIFO fill level configuration register (DFC.DFFLC) to any value between 0 and 32. Once the configured fill level is reached (in DFDRA = 0 mode after a byte was written to the DFIFO, in DFDRA = 1 mode after a byte was read from the DFIFO), the data FIFO fill level reached status bit (DFS.DFFLRF) is set and the interrupt is triggered if enabled.

The current fill level can be read at any time in the data FIFO fill level register (DFL.DFFLS).

The AVR can access the data in the DFIFO by writing or reading the DFIFO data register (DFD). The user has to set the DFC.DFDRA correctly to allow either write or read access by the AVR.

The current read and write pointer addresses can be read from the DFRP and DFWP registers, respectively. The AVR also has write access to these registers, but manual pointer manipulations must be handled with care and are mainly implemented for the purpose of debugging.

The DFIFO is reset when activated in the corresponding power reduction register PRR2.PRDF (see Sleep Modes and Active Power Reduction) or by writing a ‘1’ to the DFL.DFCLR bit.

A detailed description of the required register bits is found in Data FIFO Register Description if not stated otherwise.