3.10.5 Sleep Modes and Active Power Reduction

Sleep modes enable the application to shut down unused modules in the MCU to save power. The AVR provides various sleep modes.

To enter any of the sleep modes, the SE bit in SMCR must be written to logic ‘1’ and a SLEEP instruction must be executed. The SM[2:0] bits in the SMCR register select which sleep mode (idle, extended power save power down, power save) is activated by the AVR SLEEP instruction. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is, then, stopped for four cycles in addition to the start-up time, executes the interrupt routine and resumes execution from the instruction following SLEEP. The contents of the register file and SRAM are not altered when the device wakes up. If a reset occurs during sleep mode, the MCU wakes up and executes from the reset vector. Figure 3-57 on page 300 presents an overview of the clocks and their distribution. The following table shows the available sleep modes with the corresponding active clock domains and wake-up sources.

Idle Mode

When the SM[2:0] bits are written to “0b000”, the SLEEP instruction makes the MCU enter the idle mode, stopping the CPU but allowing the peripherals, e.g., SPI, RX/TX DSP, timer and the interrupt system to continue operating. This sleep mode basically stops CLK_CPU and CLK_NVM while allowing the other clocks to run.

Idle mode enables the MCU to wake up from externally-triggered interrupts as well as internal interrupts such as the timer overflow and a transmit buffer empty interrupt or a receive buffer full interrupt of the on-chip digital data demodulator.

Extended Power-Save Mode

When the SM[2:0] bits are written to “0b001”, the SLEEP instruction makes the MCU enter the extended power-save mode, stopping the CPU and the peripherals on the I/O bus but allowing the SPI, RX/TX DSP, timer, watchdog and the interrupt system to continue operating. This sleep mode basically stops CLK_CPU, CLK_I/O and CLK_NVM while allowing the other clocks to run.

The extended power-save mode enables the MCU to wake up from external triggered interrupts as well as internal interrupts such as the timer overflow and a transmit buffer empty interrupt or a receive buffer full interrupt of the on-chip digital data demodulator.

Power-Save Mode

When the SM[2:0] bits are written to “0b011”, the SLEEP instruction makes the MCU enter the power-save mode. In this mode, the FRC oscillator and the external input clock are stopped, while the external interrupts and the watchdog continues operation (if enabled). Only an external reset, a watchdog reset, RX DSP interrupts, an external level interrupt, or a pin change interrupt can wake up the MCU. This sleep mode basically stops all generated clocks, allowing operation of asynchronous modules only.

Power Down Mode

When the SM[2:0] bits are written to “0b010”, the SLEEP instruction makes the MCU enter power-down mode, stopping the CPU and the peripherals on the I/O bus but allowing the RX DSP interrupts, timer and the asynchronous interrupts to continue operating. This sleep mode basically stops all generated clocks, allowing operation of asynchronous modules only.