29.1 Features

  • JTAG (IEEE std. 1149.1 Compliant) Interface
  • Boundary-scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard
  • Debugger Access to:
    • All Internal Peripheral Units
    • Internal and External RAM
    • The Internal Register File
    • Program Counter
    • EEPROM and Flash Memories
  • Extensive On-chip Debug Support for Break Conditions, Including:
    • AVR Break Instruction
    • Break on Change of Program Memory Flow
    • Single Step Break
    • Program Memory Breakpoints on Single Address or Address Range
    • Data Memory Breakpoints on Single Address or Address Range
  • Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
  • On-chip Debugging Supported by Studio