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AVR Microcontroller with Core Independent Peripherals and PicoPower technology ATmega324PB

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29 JTAG Interface and On-chip Debug System
29.16 Register Description

ATmega324PB

Introduction
Feature
1 Description
2 Configuration Summary
3 Ordering Information
4 Block Diagram
5 Pin Configurations
6 I/O Multiplexing
7 General Information
8 AVR CPU Core
9 AVR Memories
10 System Clock and Clock Options
11 CFD - Clock Failure Detection mechanism
12 PM - Power Management and Sleep Modes
13 SCRST - System Control and Reset
14 INT- Interrupts
15 External Interrupts
16 I/O-Ports
17 TC0 - 8-bit Timer/Counter0 with PWM
18 TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM
19 Timer/Counter 0, 1, 3, 4 Prescalers
20 TC2 - 8-bit Timer/Counter2 with PWM and Asynchronous Operation
21 OCM - Output Compare Modulator
22 SPI – Serial Peripheral Interface
23 USART - Universal Synchronous Asynchronous Receiver Transceiver
24 USARTSPI - USART in SPI Mode
25 TWI - 2-wire Serial Interface
26 AC - Analog Comparator
27 ADC - Analog to Digital Converter
28 PTC - Peripheral Touch Controller
29 JTAG Interface and On-chip Debug System
30 BTLDR - Boot Loader Support – Read-While-Write Self-Programming
31 MEMPROG- Memory Programming
32 Electrical Characteristics
33 Typical Characteristics
34 Register Summary
35 Instruction Set Summary
36 Packaging Information
37 Errata
38 Datasheet Revision History
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29.16 Register Description

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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