11.2.2 Interrupt Line Mapping
Each of the interrupt lines is connected to one peripheral instance, as shown in the table below. Each peripheral can have one or more interrupt flags, located in the peripheral’s Interrupt Flag Status and Clear (INTFLAG) register.
The interrupt flag is set when the interrupt condition occurs. Each interrupt in the peripheral can be individually enabled by writing a one to the corresponding bit in the peripheral’s Interrupt Enable Set (INTENSET) register, and disabled by writing a one to the corresponding bit in the peripheral’s Interrupt Enable Clear (INTENCLR) register.
An interrupt request is generated from the peripheral when the interrupt flag is set and the corresponding interrupt is enabled.
The interrupt requests for one peripheral are ORed together on system level, generating one interrupt request for each peripheral. An interrupt request will set the corresponding interrupt pending bit in the NVIC interrupt pending registers (SETPEND/CLRPEND bits in ISPR/ICPR).
For the NVIC to activate the interrupt, it must be enabled in the NVIC interrupt enable register (SETENA/CLRENA bits in ISER/ICER). The NVIC interrupt priority registers IPR0-IPR7 provide a priority field for each interrupt.
| Peripheral Source (1) | Peripheral Interrupt(s) | NVIC Line |
|---|---|---|
| EIC NMI – External Interrupt Controller | NMI | NMI |
| OSCCTRL - Oscillators Controller | DPLLLDRTO | 0 |
| DPLLLTO | ||
| DPLLLCKF | ||
| DPLLLCKR | ||
| OSC48MRDY | ||
| XOSCFAIL | ||
| XOSCRDY | ||
| OSC32KCTRL - 32.768 kHz Oscillators Controller SUPC - Supply Controller | CLKFAIL | |
| OSC32KRDY | ||
| XOSC32KRDY | ||
| PAC - Protection Access Controller | ERR | |
| MCLK - Main Clock | CKRDY | |
| SUPC - Supply Controller | BVDDSRDY | |
| BODVDDDET | ||
| BODVDDRDY | ||
| WDT – Watchdog Timer | EW | 1 |
| RTC – Real Time Clock | OVF | 2 |
| CMP0 | ||
| PER7 - PER0 | ||
| EIC – External Interrupt Controller | EXTINT15 - EXTINT0 | 3 |
| FREQM – Frequency Meter | DONE | 4 |
| MCRAMC - Multi-Channel RAM Controller | DERR | 5 |
| SERR | ||
| NVMCTRL – Non-Volatile Memory Controller | FLTCAP | 6 |
| FLASHERR | ||
| DERR | ||
| SERR | ||
| ERROR | ||
| READY | ||
| DMAC - Direct Memory Access Controller | SUSP | 7 |
| TCMPL | ||
| TERR | ||
| EVSYS – Event System | EVD11 - EVD0 | 8 |
| OVR11 - OVR0 | ||
| SERCOM0 – Serial Communication Controller 0 SERCOM6 – Serial Communication Controller 6 (1) | USART: ERROR, RXBRK, CTSIC, RXS, RXC, TXC, DRE SPI: ERROR, SSL, RXC, TXC, DRE I2C Client: ERROR, DRDY, AMATCH, PREC I2C Host: ERROR, SB, MB | 9 |
| SERCOM1 – Serial Communication Controller 1 SERCOM7 – Serial Communication Controller 7 (1) | USART: ERROR, RXBRK, CTSIC, RXS, RXC, TXC, DRE SPI: ERROR, SSL, RXC, TXC, DRE I2C Client: ERROR, DRDY, AMATCH, PREC I2C Host: ERROR, SB, MB | 10 |
| SERCOM2 – Serial Communication Controller 2 | USART: ERROR, RXBRK, CTSIC, RXS, RXC, TXC, DRE SPI: ERROR, SSL, RXC, TXC, DRE I2C Client: ERROR, DRDY, AMATCH, PREC I2C Host: ERROR, SB, MB | 11 |
| SERCOM3 – Serial Communication Controller 3 | USART: ERROR, RXBRK, CTSIC, RXS, RXC, TXC, DRE SPI: ERROR, SSL, RXC, TXC, DRE I2C Client: ERROR, DRDY, AMATCH, PREC I2C Host: ERROR, SB, MB | 12 |
| SERCOM4 – Serial Communication Controller 4 (1) | USART: ERROR, RXBRK, CTSIC, RXS, RXC, TXC, DRE SPI: ERROR, SSL, RXC, TXC, DRE I2C Client: ERROR, DRDY, AMATCH, PREC I2C Host: ERROR, SB, MB | 13 |
| SERCOM5 – Serial Communication Controller 5 (1) | USART: ERROR, RXBRK, CTSIC, RXS, RXC, TXC, DRE SPI: ERROR, SSL, RXC, TXC, DRE I2C Client: ERROR, DRDY, AMATCH, PREC I2C Host: ERROR, SB, MB | 14 |
| CAN0 – Controller Area Network 0 (1) | ARA, PED, PEA, WDI, BO, EW, EP, ELO, BEU, BEC, DRX, TOO, MRAF, TSW, TEFL, TEFF, TEFW, TEFN, TFE, TCF, TC, HPM, RF1L, RF1F, RF1W, RF0L, RF0F, RF0W, RF0N | 15 |
| CAN1 – Controller Area Network 1 (1) | ARA, PED, PEA, WDI, BO, EW, EP, ELO, BEU, BEC, DRX, TOO, MRAF, TSW, TEFL, TEFF, TEFW, TEFN, TFE, TCF, TC, HPM, RF1L, RF1F, RF1W, RF0L, RF0F, RF0W, RF0N | 16 |
| TCC0 – Timer Counter for Control 0 | MC3 - MC0 | 17 |
| FAULT1 / FAULT0 / FAULTB /FAULTA | ||
| DFS | ||
| UFS | ||
| ERR | ||
| CNT | ||
| TRG | ||
| OVF | ||
| TCC1 – Timer Counter for Control 1 | MC3 - MC0 | 18 |
| FAULT1 / FAULT0 / FAULTB /FAULTA | ||
| DFS | ||
| UFS | ||
| ERR | ||
| CNT | ||
| TRG | ||
| OVF | ||
| TCC2 – Timer Counter for Control 2 | MC3 - MC0 | 19 |
| FAULT1 / FAULT0 / FAULTB /FAULTA | ||
| DFS | ||
| UFS | ||
| ERR | ||
| CNT | ||
| TRG | ||
| OVF | ||
| TC0 – Timer Counter 0, TC5 – Timer Counter 5 | MC1 - MC0 | 20 |
| ERR | ||
| OVF | ||
| TC1 – Timer Counter 1, TC6 – Timer Counter 6 | MC1 - MC0 | 21 |
| ERR | ||
| OVF | ||
| TC2 – Timer Counter 2, TC7 – Timer Counter 7 | MC1 - MC0 | 22 |
| ERR | ||
| OVF | ||
| TC3 – Timer Counter 3 | MC1 - MC0 | 23 |
| ERR | ||
| OVF | ||
| TC4 – Timer Counter 4 | MC1 - MC0 | 24 |
| ERR | ||
| OVF | ||
| ADC0 – Analog-to-Digital Converter 0 | WINMON | 25 |
| OVERRUN | ||
| RESRDY | ||
| ADC1 – Analog-to-Digital Converter 1 | WINMON | 26 |
| OVERRUN | ||
| RESRDY | ||
| AC – Analog Comparator | WIN1 - WIN0 | 27 |
| COMP3 - COMP0 | ||
| DAC – Digital-to-Analog Converter | EMPTY | 28 |
| UNDERRUN | ||
| PDEC - Position Decoder | MC1 - MC0 | 29 |
| VLC | ||
| DIR | ||
| ERR | ||
| OVF | ||
| PTC – Peripheral Touch Controller | EOC | 30 |
| WCOMP | ||
| ICM - Integrity Check Monitor | URAD | 31 |
| RSU | ||
| REC | ||
| RWC | ||
| RBE | ||
| RDM | ||
| RHC |
- Refer to the Configuration Summary chapter for the list of peripherals, peripheral instances, channels, and input/output pins present in each variant.